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Z8018x
Family MPU
User Manual
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ZiLOG WORLDWIDE HEADQUARTERS * 910 E. HAMILTON AVENUE * CAMPBELL, CA 95008 TELEPHONE: 408.558.8500 * FAX: 408.558.8300 * WWW.ZILOG.COM
Z8018x Family MPU User Manual
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact
ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
(c) 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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MANUAL OBJECTIVES
This user manual describes the features of the Z8018x Family MPUs.This manual provides basic programming information for the Z80180/Z8S180/ Z8L180. These cores and base perippheral sets are used in a large family of ZiLOG products. Below is a list of ZiLOG products that use this class of processor, along with the associated processor family.This document is also the core user manual for the following products:
Part Z80180 Z8S180 Z8L180 Z80181 Z80182 Z80S183 Z80185/195 Z80189 Family Z80180 Z8S180 Z8L180 Z80180 Z80180, Z8S180* Z8S180 Z8S180 Z8S180
* Part number-dependant
Intended Audience
This manual is written for those who program the Z8018x Family.
Manual Organization
The Z8018x Family User Manual is divided into five sections, seven appendices, and an index.
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Sections
Z8018X MPU Operation Presents features, a general description, pins descriptions, block diagrams, registers, and details of operating modes for the Z8018x MPUs. Software Architecture Provides instruction sets and CPU registers for the Z8018x MPUs. DC Characteristics Presents the DC parameters and absolute maximum ratings for the Z8X180 MPUs. AC Characteristics Presents the AC parameters for the Z8018x MPUs. Timing Diagrams Contains timing diagrams and standard test conditions for the Z8018x MPUs.
Appendices
The appendixes in this manual provide additional information applicable to the Z8018x family of ZiLOG MPUs:
* * * * * * *
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Instruction set Instruction summary table Op Code map Bus Control signal conditions in each machine cycle and interrupt conditions Operating mode summary Status signals I/O registers and ordering information
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Table of Contents
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 HALT and Low Power Operation Modes (Z80180-Class Processors Only) . . . . . . . . . . . . . . . . . . . . . . . .31 Low Power Modes (Z8S180/Z8L180 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Add-On Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 STANDBY Mode Exit wiht BUS REQUEST . . . . . . . . . . . . . . . . .38 STANDBY Mode EXit with External Interrupts . . . . . . . . . . . . . . .39 IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STANDBY-QUICK RECOVERY Mode . . . . . . . . . . . . . . . . . . . .41 Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 MMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Interrupt Acknowledge Cycle Timings . . . . . . . . . . . . . . . . . . . . . .82 Interrupt Sources During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Dynamic RAM Refresh Control . . . . . . . . . . . . . . . . . . . . . . . . . . .86 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Asynchronous Serial Communication Interface (ASCI) . . . . . . . .115
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Baud Rate Generator (Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . . . . Clocked Serial I/O Port (CSI/O) . . . . . . . . . . . . . . . . . . . . . . . . . . CSI/O Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Reload Timer (PRT) . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143 146 147 156 172
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
AC Characteristics-- Z8S180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Restart Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Data Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 Program and Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Bus and Control Signal Condition in each Machine Cycle . . . . . . . . .251 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Request Acceptances in Each Operating Mode . . . . . . . . . . . . . . . . . .281 Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Operation Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 Other Operation Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Pin Outputs in Each Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .287 Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
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List of Figures
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. 64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6 Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15 M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16 I/O Read and Write Cycles with IOC = 1 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 I/O Read and Write cycles with IOC = 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Op Code Fetch (without Wait State) Timing Diagram . . . .19 Op Code Fetch (with Wait State) Timing Diagram . . . . . .20 Memory Read/Write (without Wait State) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Memory Read/Write (with Wait State) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23 Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24 RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Bus Exchange Timing During Memory Read . . . . . . . . . . .26 Bus Exchange Timing During CPU Internal Operation . . .27 WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Memory and I/O Wait State Insertion (DCNTL - DMA/Wait Control Register) . . . . . . . . . . . . . .29 HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47.
SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Logical Address Mapping Examples . . . . . . . . . . . . . . . . . 55 Physical Address Transition . . . . . . . . . . . . . . . . . . . . . . . 56 MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Logical Memory Organization . . . . . . . . . . . . . . . . . . . . . 58 Logical Space Configuration . . . . . . . . . . . . . . . . . . . . . . . 59 Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . 64 Physical Address Generation 2 . . . . . . . . . . . . . . . . . . . . . 64 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TRAP Timing Diagram -2nd Op Code Undefined . . . . . . 71 TRAP Timing - 3rd Op Code Undefined . . . . . . . . . . . . . 72 NMI Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 INT0 Mode 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . 76 INT0 Mode 1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . 77 INT0 Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 INT0 Mode 2 Vector Acquisition . . . . . . . . . . . . . . . . . . . 79 INT0 Interrupt Mode 2 Timing Diagram . . . . . . . . . . . . . 80 INT1, INT2 Vector Acquisition . . . . . . . . . . . . . . . . . . . . 81 RETI Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 84 INT1, INT2 and Internal Interrupts Timing Diagram . . . . 86 Refresh Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . 87 DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DMA Timing Diagram-CYCLE STEAL Mode . . . . . . . 106 CPU Operation and DMA Operation DREQ0 is Programmed for Level-Sense . . . . . . . . . . . . . . . . . . . 107 Figure 48. CPU Operation and DMA Operation DREQ0 is Programmed for Edge-Sense . . . . . . . . . . . . . . . . . . . . 108
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Figure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108 Figure 50. DMA Interrupt Request Generation . . . . . . . . . . . . . . . . .114 Figure 51. NMI and DMA Operation Timing Diagram . . . . . . . . . . .115 Figure 52. ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Figure 53. DCD0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .139 Figure 54. RTS0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Figure 55. ASCI Interrupt Request Circuit Diagram . . . . . . . . . . . . .140 Figure 56. ASCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Figure 57. CSI/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Figure 58. CSI/O Interrupt Request Generation . . . . . . . . . . . . . . . . .151 Figure 59. Transmit Timing Diagram-Internal Clock . . . . . . . . . . . .153 Figure 60. Transmit Timing-External Clock . . . . . . . . . . . . . . . . . . .154 Figure 61. CSI/O Receive Timing-Internal Clock . . . . . . . . . . . . . . .155 Figure 62. CSI/O Receive Timing-External Clock . . . . . . . . . . . . . .156 Figure 63. PRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Figure 64. Timer Initialization, Count Down, and Reload Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Figure 65. Timer Output Timing Diagram . . . . . . . . . . . . . . . . . . . . .164 Figure 66. PRT Interrupt Request Generation . . . . . . . . . . . . . . . . . .164 Figure 67. E Clock Timing Diagram (During Read/Write Cycle and Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . .167 Figure 68. E Clock Timing in BUS RELEASE Mode . . . . . . . . . . . .167 Figure 69. E Clock Timing in SLEEP Mode and SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Figure 70. External Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . .169 Figure 71. Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .170 Figure 72. Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . .170 Figure 73. Example of Board Design . . . . . . . . . . . . . . . . . . . . . . . . .171
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Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 74. CPU Register Configurations . . . . . . . . . . . . . . . . . . . . . 176 Figure 75. Register Direct -- Bit Field Definitions . . . . . . . . . . . . . 181 Figure 76. Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . 181 Figure 77. Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 78. Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 79. Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 80. Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 81. AC Timing Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 82. AC Timing Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Figure 84. DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle) 201 Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Figure 87. EClockTiming(MinimumTimingExampleofPWELandPWEH) 202 Figure 88. Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 89. SLP Execution Cycle Timing Diagram . . . . . . . . . . . . . . 203 Figure 90. CSI/O Receive/Transmit Timing Diagram . . . . . . . . . . . 204 Figure 91. External Clock Rise Time and Fall Time . . . . . . . . . . . . 204 Figure 92. Input Rise Time and Fall Time (Except EXTAL, RESET) . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 93. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
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List of Tables
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .12 Memory Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Wait State Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Power-Down Modes (Z8S180/Z8L180-Class Processor Only) . . . . . . . . . . . . . .37 I/O Address Map for Z80180-Class Processors Only . . . . .44 I/O Address Map (Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . .48 State of IEF1 and IEF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 RETI Control Signal States . . . . . . . . . . . . . . . . . . . . . . . . .85 DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . . . . .89 Channel 0 Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Transfer Mode Combinations . . . . . . . . . . . . . . . . . . . . . . .99 Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . .102 DMA Transfer Request . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 ASCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .142 Clock Mode Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . .144 2^ss Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 CSI/O Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .150
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Table 23. Table 24. Table 25.
Timer Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 E Clock Timing in Each Condition . . . . . . . . . . . . . . . . . .166 Z8X180 Operating Frequencies . . . . . . . . . . . . . . . . . . . .169
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Table 26. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . .173
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 27. Table 28. Table 29. Table 30. Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . .185 Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .186 Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .187 Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .189
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 31. Z8S180 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 193
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 Instruction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 Address Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Flag Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Operations Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Arithmetic and Logical Instructions (8-bit) . . . . . . . . . . . .211 Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . .216 Arithmetic Instructions (16-bit) . . . . . . . . . . . . . . . . . . . . .221 8-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 16-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
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Table 43. Table 44. Table 45. Table 46. Table 47.
Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Stock and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . 229 I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . 235
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 48. Table 49. Table 50. 1st Op Code Map Instruction Format: XX . . . . . . . . . . . 247 2nd Op Code Map Instruction Format: CB XX . . . . . . . 249 2nd Op Code Map Instruction Format: ED XX . . . . . . . 250
Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 51. Table 52. Bus and Control Signal Condition in Each Machine Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 53. Table 54. Request Acceptances in Each Operating Mode . . . . . . . . 281 The Z80180 Types of Requests . . . . . . . . . . . . . . . . . . . . 282
Status Signals 287
Table 55. Table 56. Pin Outputs in Each Operating Mode . . . . . . . . . . . . . . . . 287 Pin Status During RESET and LOW POWER OPERATION Modes. . . . . . . . . . . . . . . . 289
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 57. Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
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Z80180, Z8S180, Z8L180 MPU Operation
FEATURES
* * * * * * * * * * *
Operating Frequency to 33 MHz On-Chip MMU Supports Extended Address Space Two DMA Channels On-Chip Wait State Generators Two Universal Asynchronous Receiver/Transmitter (UART) Channels Two 16-Bit Timer Channels On-Chip Interrupt Controller On-Chip Clock Oscillator/Generator Clocked Serial I/O Port Code Compatible with ZiLOG Z80 CPU Extended Instructions
GENERAL DESCRIPTION
Based on a microcoded execution unit and an advanced CMOS manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an 8-bit MPU which provides the benefits of reduced system costs and low power operation while offering higher performance and maintaining compatibility with a large base of industry standard software written around the ZiLOG Z8X CPU. Higher performance is obtained by virtue of higher operating frequencies, reduced instruction execution times, an enhanced instruction set, and an
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on-chip memory management unit (MMU) with the capability of addressing up to 1 MB of memory. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on-chip are several glue functions such as dynamic RAM refresh control, wait state generators, clock oscillator, and interrupt controller. Not only does the Z8X180 consume a low amount of power during normal operation, but processors with Z8S180 and Z8L180 class processors also provides two operating modes that are designed to drastically reduce the power consumption even further. The SLEEP mode reduces power by placing the CPU into a stopped state, thereby consuming less current, while the on-chip I/O device is still operating. The SYSTEM STOP mode places both the CPU and the on-chip peripherals into a stopped state, thereby reducing power consumption even further. When combined with other CMOS VLSI devices and memories, the Z8X180 provides an excellent solution to system applications requiring high performance, and low power operation. Figures 1 through 3 illustrate the three pin packages in the Z8X180 MPU family:
* * *
64-Pin Dual In-line Package (DIP), Figure 1 68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2 80-Pin Quad Flat Pack (QFP), Figure 3
Pin out package descriptions for other Z8X180-based products are covered in their respective product specifications. Figure 4 depicts the block diagram that is shared throughout all configurations of the Z8X180.
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VSS 1 XTAL 2 EXTAL 3 WAIT 4 BUSACK 5 BUSREQ 6 RESET 7 NMI 8 INT0 9 INT1 10 INT2 11 ST 12 A0 13 A1 14 A2 15 A3 16 A4 17 A5 18 A6 19 A7 20 A8 21 A9 22 A10 23 A11 24 A12 25 A13 26 A14 27 A15 28 A16 29 A17 30 A18/TOUT 31 VCC 32
64 Phi 63 RD 62 WR 61 MI 60 E 59 MREQ 58 IORQ 57 RFSH 56 HALT 55 TEND1 54 DREQ1 53 CKS 52 RXS/CTS1 51 TXS
Z8X180
50 CKA1/TEND0 49 RXA1 48 TXA1 47 CKA0/DREQ0 46 RXA0 45 TXA0 44 DCO0 43 CTS0 42 RTS0 41 D7 40 D6 39 D5 38 D4 37 D3 36 D2 35 D1 34 D0 33 VSS
Figure 1.
64-Pin DIP
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8 RESET
7 BUSREQ 6 BUSACK
5 WAIT 4 EXTAL 3 XTAL
63 MREQ
INT0 10 INT1 11 INT2 12 ST 13 A0 14 A1 15 A2 16 A3 17 VSS 18 A4 19 A5 20 A6 21 A7 22 A8 23 A9 24 A10 25 A11 26 A17 32 A18/TOUT 33 VCC 34 A19 35 VSS 36 A15 30 A16 31 D0 37 D1 38 D2 39 D3 40 A13 28 A12 27 A14 29 D4 41 D5 42 D6 43
62 IORQ 61 RFSH 60 HALT 59 TEND1 58 DREQ1 57 CKS 56 RXS/CTS1 55 TXS 54 CKA1/TEND0 53 RXA1 52 TEST 51 TXA1 50 CKA0/DREQ0 49 RXA0 48 TXA0 47 DCD0 46 CTS0 45 RTS0 44 D7
VSS VLS 68 Phi 67 RD
9 NMI
66 WR
Z8X180
Figure 2.
68-Pin PLCC
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2 1
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BUSREQ BUSACK WAIT
RESET
EXTAL NC
NMI NC NC INT0 INT1 INT2 ST A0 A1 A2 A3 VSS A4 NC A5 A6 A7 A8 A9 A10 A11 NC NC A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 10 11
72 71 70 69 68 67 66 65
80 79 78 77 76 75 74 73
RD WR MI E
MREQ IORQ
XTAL VCC VSS
Phi
64 63 62 61 60 59 58
RFSH NC NC HALT TEND1 DREQ1 CKS RXS/CTS1 TXS CKA1/TEND0 RXA1 TEST TXA1 NC CKA0/DREQ0 RXA0 TXA0 DCD0 CTS RTS0 D7 NC NC D6
Z8X180
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
A14 A15 A16
A18/TOUT VCC A19
A17 NC
A13
VSS
Figure 3.
80-Pin QFP
D0 D1
D2 D3 D4 D5
18 19 20 21 22 23 24 25
12 13 14 15 16 17
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BUSREQ
BUSACK
RESET
EXTAL
MREQ
RFSH
XTAL
HALT
IORQ
WAIT
INT0 RXA0 RTS0 CTS0 DCD0 TXA1 RXA1 VSS
NMI
WR
RD
ST
MI
E
Bus State Control Phi Timing Generator CPU
Interrupt
(16-bit)
A18/TOUT
Address Bus
Data Bus (8-bit)
16-bit Programmable Reload Timers
DMACs (2)
DREQ1 TEND1
TXA0 CKA0/DREQ0 Asynchronous SCI (Channel 0)
TXS RXS/CTS1 CKS
Clocked Serial I/O Port
MMU
Asynchronous SCI (channel 0)
CKA1/TEND0
Address Buffer
Data Buffer
VCC
A0-A19
D0-DF
Figure 4.
Z80180/Z8S180/Z8L180 Block Diagram
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PIN DESCRIPTION
A0-A19. Address Bus (Output, Active High, 3-state). A0-A19 form a 20bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The address bus enters a high impedance state during RESET and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (TOUT, selected as address output on RESET) and address line A19 is not available in DIP versions of the Z8X180. BUSACK . Bus Acknowledge (Output, Active Low). BUSACK indicates that the requesting device, the MPU address and data bus, and some control signals, have entered their high impedance state. BUSREQ. Bus Request (Input, Active Low). This input is used by external devices (such as DMA controllers) to request access to the system bus. This request has a higher priority than NMI and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and places the address and data buses, and other control signals, into the high impedance state. CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, Active High). These pins are the transmit and receive clocks for the ASCI channels. CKA0, is multiplexed with DREQ0 and CKA1 is multiplexed with TEND0. CKS. Serial Clock (Bidirectional, Active High). This line is the clock for the CSIO channel. CLOCK (PHI). System Clock (Output, Active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is equal to one-half that of the crystal or input clock frequency. CTS0, CTS1. Clear to Send 0 and 1 (Inputs, Active Low). These lines are modem control signals for the ASCI channels. CTS1 is multiplexed with RXS.
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D0-D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance state during RESET and external bus acknowledge cycles. DCD0. Data Carrier Detect 0 (Input, Active Low). This input is a programmable modem control signal for ASCI channel 0. DREQ0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a read or write operation. These inputs can be programmed to be either level- or edge-sensed. DREQ0 is multiplexed with CKA0. E. Enable Clock (Output, Active High). Synchronous machine cycle clock output during bus transactions. EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator connection. An external clock can be input to the Z8X180 on this pin when a crystal is not used. This input is Schmitt-triggered. HALT. Halt/Sleep Status (Output, Active Low). This output is asserted after the CPU has executed either the HALT or SLP instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. HALT is also used with the M1 and ST signals to decode status of the CPU machine cycle. INT0. Maskable Interrupt Request 0 (Input, Active Low). This signal is generated by external I/O devices. The CPU honors this request at the end of the current instruction cycle as long as the NMI and BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the M1 and IORQ signals become Active. INT1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low). This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI,
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BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT0, during this cycle neither the M1 or IORQ signals become Active. IORQ. I/O Request (Output, Active Low, 3-state). IORQ indicates that the address bus contains a valid I/O address for an I/O read or I/O write operation. IORQ is also generated, along with M1, during the acknowledgment of the INT0 input signal to indicate that an interrupt response vector can be placed onto the data bus. This signal is analogous to the IOE signal of the Z64180. M1. Machine Cycle 1 (Output, Active Low). Together with MREQ, M1 indicates that the current cycle is the Op Code fetch cycle of an instruction execution. Together with IORQ, M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the HALT and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR signal of the Z64180. MREQ. Memory Request (Output, Active Low, 3-state). MREQ indicates that the address bus holds a valid address for a memory read or memory write operation. This signal is analogous to the ME signal of the Z64180. NMI. Non-maskable Interrupt (Input, negative edge triggered). NMI has a higher priority than INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location 0066H. RD. Read (Output active Low, 3-state). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O or memory device must use this signal to gate data onto the CPU data bus. RFSH. Refresh (Output, Active Low). Together with MREQ, RFSH indicates that the current CPU machine cycle and the contents of the address bus must be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7-A0) contain the refresh address. This signal is analogous to the REF signal of the Z64180.
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RTS0. Request to Send 0 (Output, Active Low). This output is a programmable modem control signal for ASCI channel 0. RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals are the receive data to the ASCI channels. RXS. Clocked Serial Receive Data (Input, Active High). This line is the receiver data for the CSIO channel. RXS is multiplexed with the CTS1 signal for ASCI channel 1. ST. Status (Output, Active High). This signal is used with the M1 and HALT output to decode the status of the CPU machine cycle. Table 1 provides status summary.
Table 1. ST 0 1 1 0 0 1 Status Summary HALT 1 1 1 X1 0 0 M1 0 0 1 1 0 1 Operation CPU operation (1st Op Code fetch) CPU operation (2nd Op Code and 3rd Op Code fetch) CPU operation (MC2 except for Op Code fetch) DMA operation HALT mode SLEEP mode (including SYSTEM STOP mode)
1. X = Don't care 2. MC = Machine cycle
TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This output is asserted active during the last write cycle of a DMA operation. It is used to indicate the end of the block transfer. TEND0 in multiplexed with CKA1. TEST. Test (Output, not on DIP version). This pin is for test and must be left open.
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TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus. TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These signals are the transmitted data from the ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock. TXS. Clocked Serial Transmit Data (Output, Active High). This line is the transmitted data from the CSIO channel. WAIT. Wait (Input; Active Low). WAIT indicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. This input is used to induce additional clock cycles into the current machine cycle. The WAIT input is sampled on the falling edge of T2 (and subsequent Wait States). If the input is sampled Low, then additional Wait States are inserted until the WAIT input is sampled High, at which time execution continues. WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data bus holds valid data to be stored at the addressed I/O or memory location. XTAL. Crystal (Input, Active High). Crystal oscillator connection. This pin must be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (reference DC characteristics). Multiplexed pins are described in Table 2.
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Table 2.
Multiplexed Pin Descriptions
Multiplexed Pins
Descriptions During RESET, this pin is initialized as A18 pin. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, TOUT function is selected. If TOC1 and TOC0 bits are cleared to 0, A18 function is selected. During RESET, this pin is initialized as CKA 0 pin. If either DM1 or SM1 in DMA Mode Register (DMODE) is set to 1, DREQ0 function is always selected. During RESET, this pin is initialized as CKA1 pin. If CKA1D bit in ASCI control register ch 1 (CNTLA1) is set to 1, TEND0 function is selected. If CKA1D bit is set to 0, CKA1 function is selected. During RESET, this pin is initialized as RXS pin. If CTS1E bit in ASCI status register ch 1 (STAT1) is set to 1, CTS1 function is selected. If CTS1E bit is 0, RXS function is selected.
A18/TOUT
CKA0/DREQ0
CKA1/TEND0
RXS/CTS1
ARCHITECTURE
The Z8X180 combines a high performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller (including dynamic memory refresh), interrupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resources make up the remaining four functional blocks:
* *
Direct Memory Access (DMA) Control (2 channels) Asynchronous Serial Communications Interface (ASCI, 2 channels),
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* *
Programmable Reload Timers (PRT, 2 channels) Clock Serial I/O (CSIO) channel.
Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195) feature, in addition to these blocks, additional peripherals and are covered in their associated Product Specification Clock Generator This logic generates the system clock from either an external crystal or clock input. The external clock is divided by two and provided to both internal and external devices. Bus State Controller This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. This includes Wait State timing, RESET cycles, DRAM refresh, and DMA bus exchanges. Interrupt Controller This block monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To remain compatible with the Z80 CPU, three different interrupt modes are supported. Memory Management Unit The MMU allows the user to map the memory used by the CPU (logically only 64K) into the 1MB addressing range supported by the Z8X180. The organization of the MMU object code features compatibility with the Z80 CPU while offering access to an extended memory space. This capability is accomplished by using an effective common area - banked area scheme.
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Central Processing Unit The CPU is microcoded to provide a core that is object code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many of the instructions to execute in fewer clock cycles. DMA Controller The DMA controller provides high speed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O and I/O to I/O. Transfer modes supported are REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the full 1MB addressing range with a block length up to 64KB, and can cross over 64K boundaries. Asynchronous Serial Communications Interface (ASCI) The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communications format. Programmable Reload Timer (PRT) This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation. Clocked Serial I/O (CSIO) The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to another microprocessor or microcomputer.
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OPERATION MODES
The Z8X180 can be configured to operate like the Hitachi HD64180. This functionality is accomplished by allowing user control over the M1, IORQ, WR, and RD signals. The Operation Mode Control Register (OMCR), illustrated in Figure 5, determines the M1 options, the timing of the IORQ, RD, and WR signals, and the RETI operation. Operation Mode Control Register
Bit Bit/Field R/W Reset 7 M1E R/W 1 6 M1TE W 1 5 IOC R/W 1 4 Reserved - - 0
Note: R = Read W = Write X = Indeterminate? = Not Applicable
Figure 5.
Operation Mode Control Register
M1E (M1 Enable): This bit controls the M1 output and is set to a 1 during RESET. When M1E is 1, the M1 output is asserted Low during the Op Code fetch cycle, the INT0 acknowledge cycle, and the first machine cycle of the NMI acknowledge. This action also causes the M1 signal to be Active during both fetches of the RETI instruction sequence, and may cause corruption of the external interrupt daisy chain. Therefore, this bit must be 0 for the Z8X180. When M1E is 0 the M1 output is normally inactive and asserted Low only during the refetch of the RETI instruction sequence and the INT0 acknowledge cycle (Figure 6).
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T1 Phi WR M1
T2
T3
T1
T2
T3
Write into OMCR
Op Code Fetch
Figure 6.
M1 Temporary Enable Timing
M1TE (M1 Temporary Enable): This bit controls the temporary assertion of the M1 signal. It is always read back as a 1 and is set to 1 during RESET. This function is used to arm the internal interrupt structure of the Z80PIO. When a control word is written to the Z80PIO to enable interrupts, no enable actually takes place until the PIO sees an active M1 signal. When M1TE is 1, there is no change in the operation of the M1 signal and M1E controls its function. When M1TE is 0, the M1 output is asserted during the next Op Code fetch cycle regardless of the state programmed into the M1E bit. This situation is only momentary (one time) and the user need not reprogram a 1 to disable the function (See Figure 7). IOC: This bit controls the timing of the IORQ and RD signals. IOC is set to 1 by RESET. When IOC is 1, the IORQ and RD signals function the same as the HD64180.
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T1 Phi IORQ RD WR
T2
TW
T3
Figure 7.
I/O Read and Write Cycles with IOC = 1 Timing Diagram
When IOC is 0, the timing of the IORQ and RD signals match the timing required by the Z80 family of peripherals. The IORQ and RD signals go active as a result of the rising edge of T2. This timing allows the Z8X180 to satisfy the setup times required by the Z80 peripherals on those two signals (Figure ).
T1 Phi IORQ RD WR T2 TW T3
Figure 8.
I/O Read and Write cycles with IOC = 0 Timing Diagram
For the remainder of this document, assume that M1E is 0 and IOC is 0.
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Note:
The user must program the Operation Mode Control Register before the first I/O instruction is executed.
CPU Timing
This section explains the Z8X180 CPU timing for the following operations:
* * * * * *
Instruction (Op Code) fetch timing Operand and data read/write timing I/O read/write timing Basic instruction (fetch and execute) timing RESET timing BUSREQ/BUSACK bus exchange timing
The basic CPU operation consists of one or more Machine Cycles (MC). A machine cycle consists of three system clocks, T1, T2, and T3 while accessing memory or I/O, or it consists of one system clock (T1) during CPU internal operations. The system clock is half the frequency of the Crystal oscillator (that is, an 8-MHz crystal produces 4 MHz or 250 nsec). For interfacing to slow memory or peripherals, optional Wait States (TW) may be inserted between T2 and T3. Instruction (Op Code) Fetch Timing Figure 9 illustrates the instruction (Op Code) fetch timing with no Wait States. An Op Code fetch cycle is externally indicated when the M1 output pin is Low. In the first half of T1, the address bus (A0 -A19) is driven from the contents of the Program Counter (PC). This address bus is the translated address output of the Z8X180 on-chip MMU. In the second half of T1, the MREQ. (Memory Request) and RD (Read) signals are asserted Low, enabling the memory.
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The Op Code on the data bus is latched at the rising edge of T3 and the bus cycle terminates at the end of T3.
T1 Phi A0-A19 D0-D7 WAIT M1 MREQ RD T2 T3 T1 T2
Figure 9.
Op Code Fetch (without Wait State) Timing Diagram
Figure 10 illustrates the insertion of Wait States (TW) into the Op Code fetch cycle. Wait States (TW) are controlled by the external WAIT input combined with an on-chip programmable Wait State generator. At the falling edge of T2 the combined WAIT input is sampled. If WAIT input is asserted Low, a Wait State (TW) is inserted. The address bus, MREQ, RD and M1 are held stable during Wait States. When WAIT is sampled inactive High at the falling edge of TW, the bus cycle enters T3 and completes at the end of T3.
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T1 Phi A0-A19 D0-D7 WAIT M1 MREQ RD
T2
TW
TW
T3
T1
T2
Op Code
Figure 10.
Op Code Fetch (with Wait State) Timing Diagram
Operand and Data Read/Write Timing The instruction operand and data read/write timing differs from Op Code fetch timing in two ways:
* *
The M1 output is held inactive The read cycle timing is relaxed by one-half clock cycle because data is latched at the falling edge of T3
Instruction operands include immediate data, displacement, and extended addresses, and contain the same timing as memory data reads. During memory write cycles the MREQ signal goes active in the second half of T1. At the end of T1, the data bus is driven with the write data. At the start of T2, the WR signal is asserted Low enabling the memory. MREQ and WR go inactive in the second half of T3 followed by disabling of the write data on the data bus.
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Wait States (TW) are inserted as previously described for Op Code fetch cycles. Figure 11 illustrates the read/write timing without Wait States (Tw), while Figure 12 illustrates read/write timing with Wait States (TW).
Read Cycle T1 Phi T2 T3 T1 Write Cycle T2 T3 T1
A0-A19
Memory address
Memory address
D0-D7 WAIT MREQ RD WR
Read data
Write data
Figure 11.
Memory Read/Write (without Wait State) Timing Diagram
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Read Cycle T1 Phi T2 TW T3 T1
Write Cycle T2 TW T3
A0-A19 D0-D7 WAIT MREQ RD WR Read data
Write data
Figure 12.
Memory Read/Write (with Wait State) Timing Diagram
I/O Read/Write Timing I/O Read/Write operations differ from memory Read/Write operations in the following three ways:
* * *
The IORQ (I/O Request) signal is asserted Low instead of the MREQ signal The 16-bit I/O address is not translated by the MMU A16-A19 are held Low
At least one Wait State (TW) is always inserted for I/O read and write cycles (except internal I/O cycles). Figure 13 illustrates I/O read/write timing with the automatically inserted Wait State (TW).
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I/O Read Cycle T1 Phi A0-A19 D0-D7 WAIT IORQ RD WR I/O address Read data T2 TW T3 T1
I/O Write Cycle T2 TW T3
I/O address Write data
Figure 13.
I/O Read/Write Timing Diagram
Basic Instruction Timing An instruction may consist of a number of machine cycles including Op Code fetch, operand fetch, and data read/write cycles. An instruction may also include cycles for internal processes which make the bus IDLE. The example in Figure 14 illustrates the bus timing for the data transfer instruction LD (IX+d),g.
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1st Op Code Fetch Cycle
2nd Op Code Fetch Cycle
Displacement Read Cycle
CPU internal Operation
Memory Write Cycle
Next instruction Fetch Cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T1 T1 T1 T2 T3 T1 T2 Phi
A0-A19
PC (DDH)
PC+1 (7OH-77H)
PC+2 d
IX+d g
PC+3
D0-D7 M1 MREQ RD WR Machine Cycle
MC1 NOTE: d = displacement g = register contents MC2 MC3 MC4 MC5 MC6 MC7
Figure 14.
Instruction Timing Diagram
This instruction moves the contents of a CPU register (g) to the memory location with address computed by adding a signed 8-bit displacement (d) to the contents of an index register (IX). The instruction cycle begins with the two machine cycles to read the two byte instruction Op Code as indicated by M1 Low. Next, the instruction operand (d) is fetched.
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The external bus is IDLE while the CPU computes the effective address. Finally, the computed memory location is written with the contents of the CPU register (g). RESET Timing Figure 15 depicts the Z8X180 hardware RESET timing. If the RESET pin is Low for six or more clock cycles, processing is terminated and the Z8X180 restarts execution from (logical and physical) address 00000H.
RESET Start RESET T1 Phi RESET 6 or more clocks Op Code Fetch Cycle T2
A0-A19
High impedance
Restart address (00000H)
Figure 15.
RESET Timing Diagram
BUSREQ/BUSACK Bus Exchange Timing The Z8X180 can coordinate the exchange of control, address and data bus ownership with another bus master. The alternate bus master can request the bus release by asserting the BUSREQ (Bus Request) input Low. After the Z8X180 releases the bus, it relinquishes control to the alternate bus master by asserting the BUSACK (Bus Acknowledge) output Low. The bus may be released by the Z8X180 at the end of each machine cycle. In this context, a machine cycle consists of a minimum of three clock cycles (more if wait states are inserted) for Op Code fetch, memory read/ write, and I/O read/write cycles. Except for these cases, a machine cycle corresponds to one clock cycle.
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When the bus is released, the address (A0-A19), data (D0-D7), and control (MREQ, IORQ, RD, and WR) signals are placed in the high impedance state. Dynamic RAM refresh is not performed when the Z8X180 has released the bus. The alternate bus master must provide dynamic memory refreshing if the bus is released for long periods of time. Figure 16 illustrates BUSREQ/BUSACK bus exchange during a memory read cycle. Figure 17 illustrates bus exchange when the bus release is requested during a Z8X180 CPU internal operation. BUSREQ is sampled at the falling edge of the system clock prior to T3, T1 and Tx (BUS RELEASE state). If BUSREQ is asserted Low at the falling edge of the clock state prior to Tx, another Tx is executed.
CPU memory read cycle T1 Phi A0-A19 D0-D7 MREQ IORQ RD, WR BUSREQ BUSACK T2 TW T3 Bus release cycle TX TX T1 CPU cycle T1
Figure 16.
Bus Exchange Timing During Memory Read
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CPU Internal Operation T1 Phi A0-A19 D0-D7 MREQ IORQ RD, WR BUSREQ BUSACK T1 T1 T1
Bus Release Cycle CPU Cycle TX TX TX T1
Figure 17.
Bus Exchange Timing During CPU Internal Operation
Wait State Generator
To ease interfacing with slow memory and I/O devices, the Z8X180 uses Wait States (TW) to extend bus cycle timing. A Wait State(s) is inserted based on the combined (logical OR) state of the external WAIT input and an internal programmable wait state (TW) generator. Wait States (TW) can be inserted in both CPU execution and DMA transfer cycles. When the external WAIT input is asserted Low, Wait State(s) (TW) are inserted between T2 and T3 to extend the bus cycle duration. The WAIT input is sampled at the falling edge of the system clock in T2 or TW. If the WAIT input is asserted Low at the falling edge of the system clock in TW, another TW is inserted into the bus cycle. Note: WAIT input transitions must meet specified setup and hold times. This specification can easily be accomplished by
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externally synchronizing WAIT input transitions with the rising edge of the system clock. Dynamic RAM refresh is not performed during Wait States (TW) and thus system designs which use the automatic refresh function must consider the affects of the occurrence and duration of wait states (TW). Figure 18 depicts WAIT timing.
T1 Phi WAIT T2 TW TW T3 T1
Figure 18.
WAIT Timing Diagram
Programmable Wait State Insertion In addition to the WAIT input, Wait States (TW) can also be inserted by program using the Z8X180 on-chip Wait State generator (see Figure 19. Wait State (TW) timing applies for both CPU execution and on-chip DMAC cycles. By programming the four significant bits of the DMA/Wait Control Register (DCNTL) the number of Wait States, (TW) automatically inserted in memory and I/O cycles, can be separately specified. Bits 4 and 5 specify the number of Wait States (TW) inserted for I/O access and bits 6 and 7 specify the number of Wait States (TW) inserted for memory access. These bit pairs all 0-3 programmed Wait States for either I/O or memory access.
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Bit
7 MWI1 R/W
6 MWI0 R/W
5 MWI1 R/W
4 MWI0 R/W
Figure 19.
Memory and I/O Wait State Insertion (DCNTL - DMA/Wait Control Register)
The number of Wait States (TW) inserted in a specific cycle is the maximum of the number requested by the WAIT input, and the number automatically generated by the on-chip Wait State generator. Bit 7, 6: MWI1 MWI0, (Memory Wait Insertion) For CPU and DMAC cycles which access memory (including memory mapped I/O), zero to three Wait States may be automatically inserted depending on the programmed value in MWI1 and MWI0 as depicted in Table 3
Table 3. MW11 0 0 1 1 Memory Wait States MWI0 0 1 0 1 The Number of Wait States 0 1 2 3
Bit 5, 4: IWI1, IWI0 (I/O Wait Insertion) For CPU and DMA cycles which access external I/O (and interrupt acknowledge cycles), one to six Wait States (TW) may be automatically
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inserted depending on the programmed value in IWI1 and IWI0. Refer to Table 4.
Table 4. Wait State Insertion Th e Num be r of W ait St s ate For I NT1, I NT2 and int rnal e For I NT0 e int rrupts e For int rnal int rrupt e ack now ldge ack now ldge e e For e xt rnal I 0 e / cycls w h e n cycls e e I O re gis t rs re gis t rs / e e M 1 is L ow (Note 2) acce s s e s I I acce s s e s W0 0 1 0 1 1 2 3 4 0 (Note 1) 2 4 5 6 2 For NM I int rrupt e ack now ldge e cycls e w h e n M 1 is L ow (Note 2) 0
II W1 0 0 1 1
Note: 1.
For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States (TW) are generated. The number of Wait States inserted during access to these registers is a function of internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is, MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only three clock cycles. For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC stacking cycle, memory access timing applies.
2.
WAIT Input and RESET During RESET, MWI1, MWI0 IWI1 and IWI0, are all 1, selecting the maximum number of Wait States (TW) (three for memory accesses, four for external I/O accesses).
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Also, the WAIT input is ignored during RESET. For example, if RESET is detected while the Z8X180 is in a Wait State (TW), the Wait Stated cycle in progress is aborted, and the RESET sequence initiated. Thus, RESET has higher priority than WAIT.
HALT and Low Power Operation Modes (Z80180-Class Processors Only)
The Z80180 can operate in two different modes:
* * * *
HALT mode IOSTOP mode
and two low-power operation modes: SLEEP SYSTEM STOP
In all operating modes, the basic CPU clock (XTAL, EXTAL) must remain active. HALT Mode HALT mode is entered by execution of the HALT instruction (Op Code 76H) and has the following characteristics:
* * * * * *
The internal CPU clock remains active All internal and external interrupts can be received Bus exchange (BUSREQ and BUSACK) can occur Dynamic RAM refresh cycle (RFSH) insertion continues at the programmed interval I/O operations (ASCI, CSI/O and PRT) continue The DMAC can operate
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* *
The HALT output pin is asserted Low The external bus activity consists of repeated dummy fetches of the Op Code following the HALT instruction.
Essentially, the Z80180 operates normally in HALT mode, except that instruction execution is stopped. HALT mode can be exited in the following two ways:
*
RESET Exit from HALT Mode If the RESET input is asserted Low for at least six clock cycles, HALT mode is exited and the normal RESET sequence (restart at address 00000H) is initiated. Interrupt Exit from HALT mode When an internal or external interrupt is generated, HALT mode is exited and the normal interrupt response sequence is initiated.
*
If the interrupt source is masked (individually by enable bit, or globally by IEF1 state), the Z80180 remains in HALT mode. However, NMI interrupt initiates the normal NMI interrupt response sequence independent of the state of IEF1. HALT timing is illustrated in Figure 20.
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.
HALT Op Code Fetch Cycle T1 Phi INT1, NMI A0-A19 HALT M1 MREQ RD
HALT Op Code address HALT Op Code address + 1
HALT mode T1 T2 T3
Interrupt acknowledge cycle T1 T2
T3
Figure 20.
HALT Timing Diagram
SLEEP Mode SLEEP mode is entered by execution of the 2-byte SLP instruction. SLEEP mode contains the following characteristics:
* * * * * * * *
The internal CPU clock stops, reducing power consumption The internal crystal oscillator does not stop Internal and external interrupt inputs can be received DRAM refresh cycles stop I/O operations using on-chip peripherals continue The internal DMAC stop BUSREQ can be received and acknowledged Address outputs go High and all other control signal outputs become inactive High
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* *
Data Bus, 3-state
SLEEP mode is exited in one of two ways as described below. RESET Exit from SLEEP mode. If the RESET input is held Low for at least six clock cycles, it exits SLEEP mode and begins the normal RESET sequence with execution starting at address (logical and physical) 00000H. Interrupt Exit from SLEEP mode. The SLEEP mode is exited by detection of an external (NMI, INT0, INT2) or internal (ASCI, CSI/O, PRT) interrupt.
*
In case of NMI, SLEEP mode is exited and the CPU begins the normal NMI interrupt response sequence. In the case of all other interrupts, the interrupt response depends on the state of the global interrupt enable flag IEF1 and the individual interrupt source enable bit. If the individual interrupt condition is disabled by the corresponding enable bit, occurrence of that interrupt is ignored and the CPU remains in the SLEEP mode. Assuming the individual interrupt condition is enabled, the response to that interrupt depends on the global interrupt enable flag (IEF1). If interrupts are globally enabled (IEF1 is 1) and an individually enabled interrupt occurs, SLEEP mode is exited and the appropriate normal interrupt response sequence is executed. If interrupts are globally disabled (IEF1 is 0) and an individually enabled interrupt occurs, SLEEP mode is exited and instruction execution begins with the instruction following the SLP instruction. This feature provides a technique for synchronization with high speed external events without incurring the latency imposed by an interrupt response sequence. Figure 21 depicts SLEEP timing.
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SLP 2nd Op Code Fetch Cycle T2 Phi INT1, NMI A0-A19
SLP 2nd Op Code address
SLEEP mode T2 TS TS
Op Code Fetch or Interrupt Acknowledge Cycle T1 T2 T3
T3
T1
FFFFFH
HALT
M1
Figure 21.
SLEEP Timing Diagram
IOSTOP Mode IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control Register (ICR) to 1. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops operating. However, the CPU continues to operate. Recovery from IOSTOP mode is by resetting the IOSTOP bit in ICR to 0. SYSTEM STOP Mode SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes. SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1 followed by execution of the SLP instruction. In this mode, on-chip I/O and CPU stop operating, reducing power consumption. Recovery from SYSTEM STOP mode is the same as recovery from SLEEP mode, noting that internal I/O sources, (disabled by IOSTOP) cannot generate a recovery interrupt.
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Low Power Modes (Z8S180/Z8L180 only)
The following section is a detailed description of the enhancements to the Z8S180/L180 from the standard Z80180 in the areas of STANDBY, IDLE and STANDBY QUICK RECOVERY modes.
Add-On Features
There are five different power-down modes. SLEEP and SYSTEM STOP are inherited from the Z80180. In SLEEP mode, the CPU is in a stopped state while the on-chip I/Os are still operating. In I/O STOP mode, the onchip I/Os are in a stopped state while leaving the CPU running. In SYSTEM STOP mode, both the CPU and the on-chip I/Os are in the stopped state to reduce current consumption. The Z8S180 features two additional power-down modes, STANDBY and IDLE, to reduce current consumption even further. The differences in these power-down modes are summarized in Table 5.
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Table 5. Power-Down Modes (Z8S180/Z8L180-Class Processors Only) PowerDown Modes SLEEP I/O STOP SYSTEM STOP IDLE
On-Chip CPU Core I/O Stop Running Stop Stop Running Stop Stop Stop
Osc.
Recovery CLKOUT Source RESET, Interrupts
Recovery Time (Minimum) 1.5 Clock
Running Running Running Running Running Running Running Stop
By - Programming RESET, Interrupts RESET, Interrupts, BUSREQ RESET, Interrupts, BUSREQ 1.5 Clock 8 + 1.5 Clock
STANDBY Stop
Stop
Stop
Stop
217 + 1.5 Clock (Normal Recovery) 26 + 1.5 Clock (Quick Recovery)
IDLE and STANDBY modes are only offered in the Z8S180. The minimum recovery time can be achieved if INTERRUPT is used as the Recovery Source.
STANDBY Mode
The Z8S180/Z8L180 is designed to save power. Two low-power programmable power-down modes have been added:
* *
STANDBY mode IDLE mode
The STANDBY/IDLE mode is selected by multiplexing bits 1 and 3 of the CPU Control Register (CCR, I/O Address = 1FH). To enter STANDBY mode:
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1. Set bits 6 and 3 to 1 and 0, respectively. 2. Set the I/O STOP bits (bit 5 of ICR, I/O Address = 3FH) to 1. 3. Execute the SLEEP instruction. When the device is in STANDBY mode, it performs similar to the SYSTEM STOP mode as it exists on the Z80180-class processors, except that the STANDBY mode stops the external oscillator, internal clocks and reduces power consumption to 50 A (typical). Because the clock oscillator has been stopped, a restart of the oscillator requires a period of time for stabilization. An 18-bit counter has been added in the Z8S180Z8L180 to allow for oscillator stabilization. When the part receives an external IRQ or BUSREQ during STANDBY mode, the oscillator is restarted and the timer counts down 2 17 counts before acknowledgment is sent to the interrupt source. The recovery source must remain asserted for the duration of the 2 17 count, otherwise STANDBY restarts.
STANDBY Mode Exit with BUS REQUEST
Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the BUSREQ input is asserted. The crystal oscillator is then restarted. An internal counter automatically provides time for the oscillator to stabilize, before the internal clocking and the system clock output of the Z8S180 are resumed. The Z8S180 relinquishes the system bus after the clocking is resumed by:
* * *
3-State the address outputs A19-A0 3-State the bus control outputs MREQ, IORQ, RD, and WR Asserting BUSACK
The Z8S180 regains the system bus when BUSREQ is deactivated. The address outputs and the bus control outputs are then driven High. The STANDBY mode is exited.
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If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. If STANDBY mode is exited because of a reset or an external interrupt, the Z8S180/Z8L180-class processors remains relinquished from the system bus as long as BUSREQ is active.
STANDBY Mode EXit with External Interrupts
STANDBY mode can be exited by asserting input NMI. The STANDBY mode may also exit by asserting INT0. INT1 or INT2, depending on the conditions specified in the following paragraphs. INT0 wake-up requires assertion throughout duration of clock stabilization time (2 17 clocks). If exit conditions are met, the internal counter provides time for the crystal oscillator to stabilize, before the internal clocking and the system clock output within the Z8S180/Z8L180-class processors resume.
*
Exit with Non-Maskable Interrupts If NMI is asserted, the CPU begins a normal NMI interrupt acknowledge sequence after clocking resumes.
*
Exit with External Maskable Interrupts If an External Maskable Interrupt input is asserted, the CPU responds according to the status of the Global Interrupt Enable Flag IEF1 (determined by the ITE1 bit) and the settings of the corresponding interrupt enable bit in the Interrupt/Trap Control Register (ITC: I/O Address = 34H).
If an interrupt source is disabled in the ITC, asserting the corresponding interrupt input does not cause the Z8S180/Z8L180-class processors to exit STANDBY mode. This condition is true regardless of the state of the Global Interrupt Enable Flag IEF1.
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If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input causes the Z8S180/Z8L180-class processors to exit STANDBY mode. The CPU performs an interrupt acknowledge sequence appropriate to the input being asserted when clocking is resumed if:
* *
The interrupt input follows the normal interrupt daisy-chain protocol The interrupt source is active until the acknowledge cycle is complete
If the Global Interrupt Enable Flag IEF1 is disabled (reset to 0) and if an interrupt source is enabled in the ITC, asserting the corresponding interrupt input still causes the Z8S180/Z8L180-class processors to exit STANDBY mode. The CPU proceeds to fetch and execute instructions that follow the SLEEP instruction when clocking resumes. If the Extend Maskable Interrupt input is not active until clocking resumes, the Z8S180/Z8L180-class processors do not exit STANDBY mode. If the Non-Maskable Interrupt (NMI) is not active until clocking resumes, the Z8S180/Z8L180-class processors still exits the STANDBY mode even if the interrupt sources go away before the timer times out, because NMI is edge-triggered. The condition is latched internally when NMI is asserted Low.
IDLE Mode
IDLE mode is another power-down mode offered by the Z8S180/ Z8L180-class processors. 1. Set bits 6 and 3 to 0 and 1, respectively. 2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH to 1. 3. Execute the SLEEP instruction When the part is in IDLE mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the CLKOUT, is stopped completely. IDLE mode is exited in a similar way as STANDBY mode, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS,
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except that the 2 17 bit wake-up timer is bypassed. All control signals are asserted eight clock cycles after the exit conditions are gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered in STANDBY mode to reduce the clock recovery time in STANDBY mode from 2 17 clock cycles (4 s at 33 MHz) to 2 6 clock cycles (1.9 s at 33 MHz). This feature can only be used when providing an oscillator as clock source. To enter STANDBY-QUICK RECOVERY mode: 1. Set bits 6 and 3 to 1 and 1, respectively. 2. Set the I/O STOP bit (bit 5 of ICR, I/O Address = 3FH) to 1. 3. Execute the SLEEP instruction When the part is in STANDBY-QUICK RECOVERY mode, the operation is identical to STANDBY mode except when exit conditions are gathered, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS. The clock and other control signals are recovered sooner than the STANDBY mode. Note: If STANDBY-QUICK RECOVERY is enabled, the user must ensure stable oscillation is obtained within 64 clock cycles
Internal I/O Registers
The Z8X180 internal I/O Registers occupy 64 I/O addresses (including reserved addresses). These registers access the internal I/O modules (ASCI, CSI/O, PRT) and control functions (DMAC, DRAM refresh, interrupts, wait state generator, MMU and I/O relocation).
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To avoid address conflicts with external I/O, the Z8X180 internal I/O addresses can be relocated on 64-byte boundaries within the bottom 256 bytes of the 64KB I/O address space. I/O Control Register (ICR) ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode. I/O Control Register (ICR: 3FH)
Bit Bit/Field R/W Reset 7 IOA7 R/W 0 6 IOA6 R/W 0 5 IOSTP R/W 0 4 -- 3 -- 2 -- 1 -- 0 --
R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-6
Bit/Field R/W IOA7:6 R/W
Value
Description IOA7 and IOA6 relocate internal I/O as depicted in Figure . The high-order 8 bits of 16-bit internal I/O addresses are always 0. IOA7 and IOA6 are cleared to 0 during RESET. IOSTOP mode is enabled when IOSTP is set to 1. Normal. I/O operation resumes when IOSTP is reset to 0.
5
IOSTP
R/W
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00FFH IOA7 -- IOA6 = 1 1 00C0H 00BFH IOA7 -- IOA6 = 1 0 0080H 007FH IOA7 -- IOA6 = 0 1 0040H 003FH IOA7 -- IOA6 = 0 0 0000H
Figure 22.
I/O Address Relocation
Internal I/O Registers Address Map
The internal I/O register addresses are described in Table 6 and Table 7. These addresses are relative to the 64-byte boundary base address specified in ICR. I/O Addressing Notes The internal I/O register addresses are located in the I/O address space from 0000H to 00FFH (16-bit I/O addresses). Thus, to access the internal I/O registers (using I/O instructions), the high-order 8 bits of the 16-bit I/O address must be 0. The conventional I/O instructions (OUT (m), A/IN A, (m) / OUTI/INI, for example) place the contents of a CPU register on the high-order 8 bits of the address bus, and thus may be difficult to use for accessing internal I/O registers. For efficient internal I/O register access, a number of new instructions have been added, which force the high-order 8 bits of the 16-bit I/O
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address to 0. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM, OTDMR and TSTIO (see Instruction Set). When writing to an internal I/O register, the same I/O write occurs on the external bus. However, the duplicate external I/O write cycle exhibits internal I/O write cycle timing. For example, the WAIT input and programmable Wait State generator are ignored. Similarly, internal I/O read cycles also cause a duplicate external I/O read cycle. However, the external read data is ignored by the Z8X180. Normally, external I/O addresses should be chosen to avoid overlap with internal I/O addresses and duplicate I/O accesses.
Table 6. I/O Address Map for Z80180-Class Processors Only Address Register ASCI ASCI Control Register A Ch 0 ASCI Control Register A Ch 1 ASCI Control Register B Ch 0 ASCI Control Register B Ch 1 ASCI Status Register Ch 0 ASCI Status Register Ch 1 ASCI Transmit Data Register Ch 0 ASCI Transmit Data Register Ch 1 ASCI Receive Data Register Ch 0 ASCI Receive Data Register Ch 1 CSI/O CSI/O Control Register Mnemonic CNTLA0 CNTLA1 CNTLB0 CNTLB1 STAT0 STAT1 TDR0 TDR1 RDR0 RDR1 CNTR Binary XX000000 XX000001 XX000010 XX000011 XX000100 XX000101 XX000110 XX000111 XX001000 XX001001 XX001010 XX1011 Hex 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Page 125 128 132 132 120 123 118 118 119 119 147 149
CSI/O Transmit/Receive Data Register TRD
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Table 6.
I/O Address Map for Z80180-Class Processors Only
(Continued) Address
Register Timer Data Register Ch 0 L Data Register Ch 0 H Reload Register Ch 0 L Reload Register Ch 0 H Timer Control Register Reserved
Mnemonic TMDR0L TMDR0H RLDR0L RLDR0H TCR
Binary XX001100 XX001101 XX001110 XX001111 XX010000 XX010001
Hex 0CH 0DH 0EH 0FH 10H 11H
Page 159 159 159 159 161
XX010011 Data Register Ch 1 L Data Register Ch 1 H Reload Register Ch 1 L Reload Register Ch 1 H Others Free Running Counter Reserved TMDR1L TMDR1H RLDR1L RLDR1H FRC XX010100 XX010101 XX010110 XX010111 XX011000 XX011001
13H 14H 15H 16H 17H 18H 19H 160 160 159 159 172
XX011111
1FH
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Table 6.
I/O Address Map for Z80180-Class Processors Only
(Continued) Address
Register DMA DMA Source Address Register Ch 0L DMA Source Address Register Ch 0H DMA Source Address Register Ch 0B
Mnemonic SAR0L SAR0H SAR0B
Binary XX100000 XX100001 XX100010 XX100011 XX100100 XX100101 XX100110 XX100111 XX101000 XX101001 XX101010 XX101011 XX101100 XX101101
Hex 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H
Page 93 93 93 94 94 94 94 94 94 94 94 102 102
DMA Destination Address Register Ch DAR0L 0L DMA Destination Address Register Ch DAR0H 0H DMA Destination Address Register Ch DAR0B 0B DMA Byte Count Register Ch 0L DMA Byte Count Register Ch 0H BCR0L BCR0H
DMA Memory Address Register Ch 1L MAR1L DMA Memory Address Register Ch 1H MAR1H DMA Memory Address Register Ch 1B MAR1B DMA I/0 Address Register Ch 1L DMA I/0 Address Register Ch 1H Reserved DMA Byte Count Register Ch 1L DMA Byte Count Register Ch 1H DMA Status Register DMA Mode Register DMA/WAIT Control Register BCR1L BCR1H DSTAT DMODE DCNTL IAR1L IAR1H
XX101110 XX101111 XX110000 XX110001 XX110010
94 94 95 97 101
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Table 6.
I/O Address Map for Z80180-Class Processors Only
(Continued) Address
Register INT IL Register (Interrupt Vector Low Register) INT/TRAP Control Register Reserved Refresh Refresh Control Register Reserved MMU MMU Common Base Register MMU Bank Base Register MMU Common/Bank Area Register I/O Reserved
Mnemonic IL ITC
Binary XX110011 XX110100 XX110101
Hex 33H 34H 35H 36H 37H 38H 39H 3AH 3BH
Page 67 68
RCR
XX110110 XX110111
88
CBR BBR CBAR
XX111000 XX111001 XX111010 XX111011
61 62 60
XX111101 Operation Mode Control Register I/O Control Register OMCR ICR XX111110 XX111111
3DH 3EH 3FH 15 42
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) Address Register ASCI ASCI Control Register A Ch 0 ASCI Control Register A Ch 1 ASCI Control Register B Ch 0 ASCI Control Register B Ch 1 ASCI Status Register Ch 0 ASCI Status Register Ch 1 ASCI Transmit Data Register Ch 0 ASCI Transmit Data Register Ch 1 ASCI Receive Data Register Ch 0 ASCI Receive Data Register Ch 1 ASCI0 Extension Control Register 0 ASCI1 Extension Control Register 1 ASCI0 Time Constant Low ASCI0 Time Constant High ASCI1 Time Constant Low ASCI1 Time Constant High CSI0 CSI0 Control Register CSI0 Transmit/Receive Data Register Mnemonic CNTLA0 CNTLA1 CNTLB0 CNTLB1 STAT0 STAT1 TDR0 TDR1 RDR0 RDR1 ASEXT0 ASEXT1 ASTC0L ASTC0H ASCT1L ASCT1H CNTR TRD Binary XX000000 XX000001 XX000010 XX000011 XX000100 XX000101 XX000110 XX000111 XX001000 XX001001 XX010010 XX010011 XX011010 XX001011 XX001100 XX001101 XX001010 XX1011 Hex 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 12H 13H 1AH 1BH 1CH 1DH 0AH 0BH Page 125 128 132 132 120 123 118 118 119 119 135 136 137 137 138 138 147 149
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
(Continued) Address
Register Timer Data Register Ch 0 L Data Register Ch 0 H Reload Register Ch 0 L Reload Register Ch 0 H Timer Control Register Reserved Data Register Ch 1 L Data Register Ch 1 H Reload Register Ch 1 L Reload Register Ch 1 H Others Free Running Counter Reserved
Mnemonic TMDR0L TMDR0H RLDR0L RLDR0H TCR
Binary XX001100 XX001101 XX001110 XX001111 XX010000 XX010001
Hex 0CH 0DH 0EH 0FH 10H 11H 14H 15H 16H 17H 18H 19H
Page 159 159 159 159 161
TMDR1L TMDR1H RLDR1L RLDR1H FRC
XX010100 XX010101 XX010110 XX010111 XX011000 XX011001
160 160 160 160 172
XX011111 Clock Multiplier Register CPU Control Register CMR CCR XX011110 XX011111
1DH 1EH 1FH 52 53
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
(Continued) Address
Register DMA DMA Source Address Register Ch 0L DMA Source Address Register Ch 0H DMA Source Address Register Ch 0B
Mnemonic SAR0L SAR0H SAR0B
Binary XX100000 XX100001 XX100010 XX100011 XX100100 XX100101 XX100110 XX100111 XX101000 XX101001 XX101010 XX101011 XX101100 XX101101 XX101110 XX101111 XX110000 XX110001 XX110010
Hex 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H
Page 93 93 93 94 94 94 94 94 94 94 94 102 102 94 94 94 95 97 101
DMA Destination Address Register Ch DAR0L 0L DMA Destination Address Register Ch DAR0H 0H DMA Destination Address Register Ch DAR0B 0B DMA Byte Count Register Ch 0L DMA Byte Count Register Ch 0H BCR0L BCR0H
DMA Memory Address Register Ch 1L MAR1L DMA Memory Address Register Ch 1H MAR1H DMA Memory Address Register Ch 1B MAR1B DMA I/O Address Register Ch 1L DMA I/O Address Register Ch 1H DMA I/O Address Register Ch 1 DMA Byte Count Register Ch 1L DMA Byte Count Register Ch 1H DMA Status Register DMA Mode Register DMA/WAIT Control Register IAR1L IAR1H IAR1B BCR1L BCR1H DSTAT DMODE DCNTL
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Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued) Address Register INT IL Register (Interrupt Vector Low Register) INT/TRAP Control Register Reserved Refresh Refresh Control Register Reserved MMU MMU Common Base Register MMU Bank Base Register MMU Common/Bank Area Register I/O Reserved CBR BBR CBAR RCR Mnemonic IL ITC Binary XX110011 XX110100 XX110101 XX110110 XX110111 XX111000 XX111001 XX111010 XX111011 Hex 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 61 62 60 88 Page 67 68
XX111101 Operation Mode Control Register I/O Control Register OMCR ICR XX111110 XX111111
3DH 3EH 3FH 15 42
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Clock Multiplier Register (CMR: 1EH) (Z8S180/L180-Class Processors Only)
Bit Bit/Field R/W Reset 7 X2 R/W 0 6 Reserved ? 1 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W X2 Clock Multiplier Mode Reserved R/W
Value 0 1
Description X2 Clock Multiplier Mode Disable Enable Reserved
6-0
?
?
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CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)
Bit Bit/Field 7 Clock Divide 6 STAND BY/ IDLE Enable R/W 0 5 BREXT 4 LNPHI 3 STAND BY/ IDLE Enable R/W 0 2 LNIO 1 LNCPU CTL 0 LNAD/ DATA
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7 6
Bit/Field Clock Divide STANDBY /IDLE Mode
R/W R/W R/W
Value Description 0 1 00 01 10 11 XTAL/2 XTAL/1 In conjunction with Bit 3 No STANDBY IDLE after SLEEP STANDBY after SLEEP STANDBY after SLEEP 64 Cycle Exit (Quick Recovery) Ignore BUSREQ in STANDBY/IDLE STANDBY/IDLE exit on BUSREQ Standard Drive 33% Drive on EXTPHI Clock In conjunction with Bit 6 No STANDBY IDLE after SLEEP STANDBY after SLEEP STANDBY after SLEEP 64 Cycle Exit (Quick Recovery)
5 4 3
BREXT LNPHI STANDBY /IDLE Mode
R/W R/W R/W
0 1 0 1 00 01 10 11
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Bit Position 2 1 0
Bit/Field LNIO LNCPUCTL LNAD/ DATA
R/W R/W R/W R/W
Value Description 0 1 0 1 0 1 Standard Drive 33% Drive on certain external I/O Standard Drive 33% Drive on CPU control signals Standard Drive 33% drive on A10-A0, D7-D0
Memory Management Unit (MMU)
The Z8X180 features an on-chip MMU which performs the translation of the CPU 64KB (16-bit addresses 0000H to FFFFH) logical memory address space into a 1024KB (20-bit addresses 00000H to FFFFFH) physical memory address space. Address translation occurs internally in parallel with other CPU operation. Logical Address Spaces The 64KB CPU logical address space is interpreted by the MMU as consisting of up to three separate logical address areas, Common Area 0, Bank Area, and Common Area 1. As depicted in Figure 23, a variety of logical memory configurations are possible. The boundaries between the Common and Bank Areas can be programmed with 4KB resolution.
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Common Area 1 Bank Area
Common Area 1
Common Area 1
Common Area 1
Common Area 0
Bank Area
Common Area 0
Figure 23.
Logical Address Mapping Examples
Logical to Physical Address Translation Figure 24 illustrates an example in which the three logical address space portions are mapped into a 1024KB physical address space. The important points to note are that Common and Bank Areas can overlap and that Common Area 1 and Bank Area can be freely relocated (on 4KB physical address boundaries). Common Area 0 (if it exists) is always based at physical address 00000H.
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FFFFFH
z FFFFH Common Area 1 Bank Area Common Area 0 0000H + Common Base + + xyz Logical Address Space x Bank Base y 0
00000H Physical Address Space
Figure 24.
Physical Address Transition
MMU Block Diagram The MMU block diagram is depicted in Figure 25. The MMU translates internal 16-bit logical addresses to external 20-bit physical addresses.
Internal Address/Data Bus 4 LA12-- LA15 MMU Common/Bank Area Register; CBAR (8) Memory Management Unit 8 PA12-- PA19 LA: Logical Address PA: Physical Address MMU Common Base Register; CBR (8) MMU Bank Base Register; BBR (8)
Figure 25.
MMU Block Diagram
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Whether address translation (Figure 26) takes place depends on the type of CPU cycle as follows.
*
Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector fetch, and software interrupt restarts.
*
I/O Cycles The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O address space corresponds directly with the 16-bit physical I/O address space. The four high-order bits (A16-A19) of the physical address are always 0 during I/O cycles.
LA15 " 0000" PA19 PA16 PA15 PA0 Physical Address LA0 Logical Address
Figure 26.
I/O Address Translation
*
DMA Cycles When the Z8X180 on-chip DMAC is using the external bus, the MMU is physically bypassed. The 20-bit source and destination registers in the DMAC are directly output on the physical address bus (A0-A19).
MMU Registers Three MMU registers are used to program a specific configuration of logical and physical memory.
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* * *
MMU Common/Bank Area Register (CBAR) MMU Common Base Register (CBR) MMU Bank Base Register (BBR)
CBAR is used to define the logical memory organization, while CBR and BBR are used to relocate logical areas within the 1024KB physical address space. The resolution for both setting boundaries within the logical space and relocation within the physical space is 4KB. The CA field of CBAR determines the start address of Common Area 1 (Upper Common) and by default, the end address of the Bank Area. The BA field determines the start address of the Bank Area and by default, the end address of Common Area 0 (Lower Common). The CA and BA fields of CBAR may be freely programmed subject only to the restriction that CA may never be less than BA. Figures 27 and 28 illustrate examples of logical memory organizations associated with different values of CA and BA.
Common Area 1 Bank Area Bank Area Common Area 0 Common Area 0 Common Area 1 Common Area 1
Common Area 1
Common Area 1 Common Area 1 Common Area 1 Common Area 1 Lower Limit Address Lower lImit Address Lower Limit Address Lower Limit Address > > = = Bank Area Bank Area Bank Area Bank Area Lower Limit Address Lower lImit Address Lower Limit Address Lower Limit Address > = > = 0000H 0000H 0000H 0000H (RESET Condition)
Figure 27.
Logical Memory Organization
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FFFFH MMU Common/Bank Area Register 1 10 1 D D000H CFFFH Common Area 1
D7 D6 D5 D4
Bank Area MMU Common/Bank Area Register 0 1 0 0 4 4000H 3FFFH Common Area 0 0000H
D3 D2 D1 D0
Figure 28.
Logical Space Configuration (Example)
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MMU Register Description
MMU Common/Bank Area Register (CBAR) CBAR specifies boundaries within the Z8X180 64KB logical address space for up to three areas; Common Area 0, Bank Area and Common Area 1. MMU Common/Bank Area Register (CBAR: 3AH)
Bit Bit/Field R/W Reset 7 CA3 R/W 1 6 CA2 R/W 1 5 CA1 R/W 1 4 CA0 R/W 1 3 BA3 R/W 0 2 BA2 R/W 0 1 BA1 R/W 0 0 BA0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-4
Bit/Field R/W CA7-4 R/W
Value
Description CA specifies the start (low) address (on 4KB boundaries) for the Common Area 1. This also determines the last address of the Bank Area. BA specifies the start (low) address (on 4KB boundaries) for the Bank Area. This also determines the last address of the Common Area 0.
3-0
BA3-0
R/W
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MMU Common Base Register (CBR) CBR specifies the base address (on 4K boundaries) used to generate a 20bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0 during RESET. MMU Common Base Register (CBR: 38H)
Bit Bit/Field R/W Reset 7 CB7 R/W 0 6 CB6 R/W 0 5 CB5 R/W 0 4 CB4 R/W 0 3 CB3 R/W 0 2 CB2 R/W 0 1 CB1 R/W 0 0 CB0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-0
Bit/Field R/W CB7-0 R/W
Value
Description CBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Common Area 1 accesses.
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MMU Bank Base Register (BBR) BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses. All bits of BBR are reset to 0 during RESET. MMU Bank Base Register (BBR: 39H)
Bit Bit/Field R/W Reset 7 BB7 R/W 0 6 BB6 R/W 0 5 BB5 R/W 0 4 BB4 R/W 0 3 BB3 R/W 0 2 BB2 R/W 0 1 BB1 R/W 0 0 BB0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-0
Bit/Field BB7-0
R/W R/W
Value Description BBR specifies the base address (on 4KB boundaries) used to generate a 20-bit physical address for Bank Area accesses.
Physical Address Translation Figure 29 illustrates the way in which physical addresses are generated based on the contents of CBAR, CBR and BBR. MMU comparators classify an access by logical area as defined by CBAR. Depending on which of the three potential logical areas (Common Area 1, Bank Area, or Common Area 0) is being accessed, the appropriate 8- or 7-bit base address is added to the high-order 4 bits of the logical address, yielding a 19- or 20-bit physical address. CBR is associated with Common Area 1 accesses. Common Area 0, if defined, is always based at physical address
00000H.
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MMU and RESET During RESET, all bits of the CA field of CBAR are set to 1 while all bits of the BA field of CBAR, CBR and BBR are reset to 0. The logical 64KB address space corresponds directly with the first 64KB 0000H to FFFFH) of the 1024KB 00000H. to FFFFFH) physical address space. Thus, after RESET, the Z8X180 begins execution at logical and physical address 0. MMU Register Access Timing When data is written into CBAR, CBR or BBR, the value is effective from the cycle immediately following the I/O write cycle which updates these registers. During MMU programming insure that CPU program execution is not disrupted. The next cycle following MMU register programming is normally an Op Code fetch from the newly translated address. One technique is to localize all MMU programming routines in a Common Area that is always enabled.
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MMU Common/ Bank Area Register
4 4
15
12 11
0
D7 -- D4
MMU Common/ Bank Area Register 4
Comparator
Logical Address (64K)
D3 -- D0
MMU Common Base Reg. MMU Bank Base Reg.
8 4
00000000
Adder
8
Physical Address (512 k or 1 M)
(19) 18
12 11
0
Figure 29.
Physical Address Generation
Logical Address (64 k)
(7) 15 12 11 0
43
0
Base Register (8 bit) (1 M) Physical Address
(19) 18 16 15 12 11 0
Figure 30.
Physical Address Generation 2
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Note:
Packages not containing an A19 pin or situations using TOUT instead of A18 yield an address capable of only addressing 512K of physical space.
Interrupts
The Z8X180 CPU has twelve interrupt sources, 4 external and 8 internal, with fixed priority. (Reference Figure 31.) This section explains the CPU registers associated with interrupt processing, the TRAP interrupt, interrupt response modes, and the external interrupts. The detailed discussion of internal interrupt generation (except TRAP) is presented in the appropriate hardware section (that is, PRT, DMAC, ASCI, and CSI/O).
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Lower (11) Priority (12) Higher Priority TRAP (Undefined Op Code Trap) NMI (Non Maskable Interrupt) INT0 (Maskable Interrupt Level 0) INT1 (Maskable Interrupt Level 1) INT2 (Maskable Interrupt Level 2) Timer 0 Timer 1 DMA channel 0 DMA channel 1 Clocked Serial I/O Port Asynchronous SCI channel 0 Asynchronous SCI channel 1 Internal Interrupt External Interrupt
Internal Interrupt
Figure 31.
Interrupt Sources
Interrupt Control Registers and Flags. The Z8X180 has three registers and two flags which are associated with interrupt processing.
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Function Interrupt Vector High Interrupt Vector Low Interrupt/Trap Control
Name I IL ITC
Access Method LD A,I and LD I, A instructions I/O instruction (addr = 33H) I/O instruction (addr = 34H)
Interrupt Enable Flag 1,2 IEF1, IEF2 El and DI
Interrupt Vector Register (I)
Mode 2 for INT0 external interrupt, INT1 and INT2 external interrupts, and all internal interrupts (except TRAP) use a programmable vectored technique to determine the address at which interrupt processing starts. In response to the interrupt a 16-bit address is generated. This address accesses a vector table in memory to obtain the address at which execution restarts. While the method for generation of the least significant byte of the table address differs, all vectored interrupts use the contents of I as the most significant byte of the table address. By programming the contents of I, vector tables can be relocated on 256 byte boundaries throughout the 64KB logical address space. Note: I is read/written with the LD A, I and LD I, A instructions rather than I/O (IN, OUT) instructions. I is initialized to 00H during RESET.
Interrupt Vector Low Register
This register determines the most significant three bits of the low-order byte of the interrupt vector table address for external interrupts INT1 and INT2 and all internal interrupts (except TRAP). The five least significant bits are fixed for each specific interrupt source. By programming IL, the
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vector table can be relocated on 32 byte boundaries. IL is initialized to 00H during RESET. Interrupt Vector Low Register (IL: 33H)
Bit Bit/Field R/W Reset 7 IL7 R/W 00H 6 IL6 R/W 00H 5 IL5 R/W 00H 4 3 2 ?
?
1
0
?
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-5
Bit/Field IL7-5
R/W R/W
Value Description The IL register is an internal I/O register which is programmed with the OUT0 instruction and can be read using the IN0 instruction. Interrupt source dependent code
4-0
?
N/A
INT/TRAP Control Register (ITC)
ITC is used to handle TRAP interrupts and to enable or disable the external maskable interrupt inputs INT0, INT1 and INT2.
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INT/TRAP Control Register (ITC: 34H)
Bit Bit/Field R/W Reset 7 TRAP R/W 0 6 UFO R 0 5 4 ?
N/A
3
2 ITE2 R/W 0
1 ITE1 R/W 0
0 ITE0 R/W 1
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field TRAP
R/W R/W
Value Description This bit is set to 1 when an undefined Op Code is fetched. TRAP can be reset under program control by writing it with 0, however, it cannot be written with 1 under program control. Undefined Fetch Object (bit 6). When a TRAP interrupt occurs the contents of UFO allow determination of the starting address of the undefined instruction. This action is necessary since the TRAP may occur on either the second or third byte of the Op Code. UFO allows the stacked PC value to be correctly adjusted. If UFO = 0, the first Op Code should be interpreted as the stacked PC-1. If UFO = 1, the first Op Code address is stacked PC-2. Interrupt Enable -- ITE2, ITE1 and ITE0 enable and disable the external interrupt inputs INT2, INT1 and INT0, respectively. If reset to 0, the interrupt is masked.
6
UFO
R
2-0
ITE2-0
R/W
Interrupt Enable Flag 1,2 (IEF1, IEF2) IEF1 controls the overall enabling and disabling of all internal and external maskable interrupts (that is, all interrupts except NMI and TRAP.
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If IEF1 is 0, all maskable interrupts are disabled. IEF1 can be reset to 0 by the DI (Disable Interrupts) instruction and set to 1 by the El (Enable Interrupts) instruction. The purpose of IEF2 is to correctly manage the occurrence of NMI. During NMI, the prior interrupt reception state is saved and all maskable interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1 cleared to 0). At the end of the NMI interrupt service routine, execution of the RETN (Return from Non-maskable Interrupt) automatically restores the interrupt receiving state (by copying IEF2 to IEF1) prior to the occurrence of NMI. Table 8 describes how the IEF2 state can be reflected in the P/V bit of the CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8. CPU Operation RESET NMI RETN State of IEF1 and IEF2
IEF1 0 0 IEF2
IEF2 0 IEF1
REMARKS Inhibits the interrupt except NMI and TRAP. Copies the contents of IEF1 to IEF2
not affected Returns from the NMI service routine. 0 Inhibits the interrupt except NMI end TRAP
Interrupt except 0 NMI end TRAP RETI TRAP EI
not affected not affected not affected not affected 1 1
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Table 8. CPU Operation DI LD A, I LID A, R
State of IEF1 and IEF2 (Continued)
IEF1 0
IEF2 0
REMARKS
not affected not affected Transfers the contents of IEF1 to P/V not affected not affected Transfers the contents of IEF1 to P/V
TRAP Interrupt The Z8X180 generates a non-maskable (not affected by the state of IEF1) TRAP interrupt when an undefined Op Code fetch occurs. This feature can be used to increase software reliability, implement an extended instruction set, or both. TRAP may occur during Op Code fetch cycles and also if an undefined Op Code is fetched during the interrupt acknowledge cycle for INT0 when Mode 0 is used. When a TRAP interrupt occurs the Z8X180 operates as follows: 1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1. 2. The current PC (Program Counter) value, reflecting location of the undefined Op Code, is saved on the stack. 3. The Z8X180 vectors to logical address 0. Note that if logical address 0000H is mapped to physical address 00000H. the vector is the same as for RESET. In this case, testing the TRAP bit in ITC reveals whether the restart at physical address 00000H was caused by RESET or TRAP. The state of the UFO (Undefined Fetch Object) bit in ITC allows TRAP manipulation software to correctly adjust the stacked PC, depending on whether the second or third byte of the Op Code generated the TRAP. If UFO is 0, the starting address of the invalid instruction is equal to the
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stacked PC-1. If UFO is 1, the starting address of the invalid instruction is equal to the stacked PC-2. Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be inserted just after TTP state which is inserted for TRAP interrupt sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and Figure illustrates Trap Timing - 3rd Op Code undefined.
Restart from 0000H 2nd Op Code Fetch Cycle PC Stacking Op Code Fetch Cycle
T1
T2
T3
Ti
Ti
Ti
Ti
Ti
T1
T2
T3
T1
T2
T3
T1
T2
T3
Phi A0-A19 D0-D7
Undefined Op Code PC SP-1 PCH SP-2 PCL 0000H
MI MREQ RD WR
Figure 32.
TRAP Timing Diagram -2nd Op Code Undefined
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3rd Op Code Fetch Cycle
Memory Read Cycle
Restart from 0000H PC stacking Op Code fetch cycle T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi A0-A19 D0-D7 MI MREQ RD WR
T1 T2 T3
T1 T2 TTP T3 T1 Ti
Ti
Ti
PC Undefined Op Code
IX+d, IY+d
SP-1 PCH
SP-2 PCL
0000H
Figure 33.
TRAP Timing - 3rd Op Code Undefined
External Interrupts The Z8X180 features four external hardware interrupt inputs:
* * * *
NMI-Non-maskable interrupt INT0-Maskable Interrupt Level 0 INT1-Maskable Interrupt Level 1 INT2-Maskable Interrupt Level 2
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3 different software programmable interrupt response modes-- Mode 0, Mode 1 and Mode 2. NMI - Non-Maskable Interrupt The NMI interrupt input is edge-sensitive and cannot be masked by software. When NMI is detected, the Z8X180 operates as follows:
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1. DMAC operation is suspended by the clearing of the DME (DMA Main Enable) bit in DCNTL. 2. The PC is pushed onto the stack. 3. The contents of IEF1 are copied to IEF2. This saves the interrupt reception state that existed prior to NMI. 4. IEF1 is cleared to 0. This disables all external and internal maskable interrupts (that is, all interrupts except NMI and TRAP). 5. Execution commences at logical address 0066H. The last instruction of an NMI service routine must be RETN (Return from Non-maskable Interrupt). This restores the stacked PC, allowing the interrupted program to continue. Furthermore, RETN causes IEF2 to be copied to IEF1, restoring the interrupt reception state that existed prior to NMI. Note: NMI, because it can be accepted during Z8X180 on-chip DMAC operation, can be used to externally interrupt DMA transfer. The NMI service routine can reactivate or abort the DMAC operation as required by the application.
For NMI, take special care to insure that interrupt inputs do not overrun the NMI service routine. Unlimited NMI inputs without a corresponding number of RETN instructions eventually cause stack overflow. Figure 34 depicts the use of NMI and RETN while Figure 35 details NMI response timing. NMI is edge sensitive and the internally latched NMI falling edge is held until it is sampled. If the falling edge of NMI is latched before the falling edge of the clock state prior to T3 or T1 in the last machine cycle, the internally latched NMI is sampled at the falling edge of the clock state prior to T3 or T1 in the last machine cycle and NMI acknowledge cycle begins at the end of the current machine cycle.
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Main Program
EF1 0 PCH PCL
EF2 EF1 (SP-1) (SP-2)
0066H
NMI EF1 EF2 PCL (SP) PCH (SP+1)
NMI Interrupt Service Program
RETN
Figure 34.
NMI Use
Last MC
NMI acknowledge cycle PC is pushed onto stack Restart from 0066H Op Code fetch T1 T1 T3 Ti T1 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi NMI A0-A19
PC SP-1 SP-2 0066H Instruction
D0-D7 MI MREQ RD WR
PCH
PCL
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Figure 35.
NMI Timing
INT0 - Maskable Interrupt Level 0
The next highest priority external interrupt after NMI is INT0. INT0 is sampled at the falling edge of the clock state prior to T3 or T1 in the last machine cycle. If INT0 is asserted LOW at the falling edge of the clock state prior to T3 or T1 in the last machine cycle, INT0 is accepted. The interrupt is masked if either the IEF1 flag or the ITEO (Interrupt Enable 0) bit in ITC are reset to 0. After RESET the state is as follows: 1. IEF1 is 0, so INT0 is masked 2. ITE0 is 1, so INT0 is enabled by execution of the El (Enable Interrupts) instruction The INT0 interrupt is unique in that 3 programmable interrupt response modes are available - Mode 0, Mode 1 and Mode 2. The specific mode is selected with the IM 0, IM 1 and IM 2 (Set Interrupt Mode) instructions. During RESET, the Z8X180 is initialized to use Mode 0 for INT0. The 3 interrupt response modes for INT0 are:
* * *
Mode 0-Instruction fetch from data bus Mode 1-Restart at logical address 0038H Mode 2-Low-byte vector table address fetch from data bus
INT0 Mode 0
During the interrupt acknowledge cycle, an instruction is fetched from the data bus (DO-D7) at the rising edge of T3. Often, this instruction is one of the eight single byte RST (RESTART) instructions which stack the PC and restart execution at a fixed logical address. However, multibyte instructions can be processed if the interrupt acknowledging device can provide a multibyte response. Unlike all other interrupts, the PC is not automatically stacked:
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Last MC
INT0 acknowledge cycle
RST instruction execution PC is pushed onto stack
T1
T2
* TW TW* T3
Ti
Ti
T1
T2
T3
T1
T2
T3
Phi INT0 A0-A19
PC SP-1 SP-2
M1 MREQ
RD WR IORQ
RST instruction
D0-D7
MC: Machine Cycle
PCH
PCL
*Two Wait States are automatically inserted
Note: The TRAP interrupt occurs if an invalid instruction is fetched during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Figure 36. INT0 Mode 0 Timing Diagram
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution restarts at logical address 0038H. Both IEF1 and IEF2 flags are reset to 0,
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disabling all maskable interrupts. The interrupt service routine normally terminates with the EI (Enable Interrupts) instruction followed by the RETI (Return from Interrupt) instruction, to reenable the interrupts. Figure 37 depicts the use of INT0 (Mode 1) and RETI for the Mode 1 interrupt sequence.
Figure 37. INT0 Mode 1 Interrupt Sequence
Main Program 0 EF1, EF2 PCH (SP-1) PCL (SP-2) 0038H
INT0 (Mode 1) PCL (SP) PCH (SP+1)
INT0 (Mode 1) Interrupt Service Program E1 (1 1EF1, 1EF2) RETI
Figure 38 illustrates INT0 Mode 1 Timing.
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Last MC
INT0 Acknowledge Cycle PC is pushed onto stack T1 T2 TW* TW* T3 T1 T2 T3 T1 T2 T3
Op Code Fetch Cycle
T1
T2
T3
Phi INT0 A0-A19 M1 MREQ IORQ RD WR D0-D7 ST
*Two Wait States are automatically inserted PCH PCL PC SP-1 SP-2 0038H
Figure 38.
INT0 Mode 1 Timing
INT0 Mode 2
This method determines the restart address by reading the contents of a table residing in memory. The vector table consists of up to 128 two-byte restart addresses stored in low byte, high byte order.
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The vector table address is located on 256 byte boundaries in the 64KB logical address space programmed in the 8-bit Interrupt Vector Register (1). Figure 39 depicts the INT0 Mode 2 Vector acquisition.
Memory 16-bit Vector Interrupt Vector Register I 8-bit on Data Bus High-order 8 bits of starting address Low-order 8 bits of starting address
Vector + 1 Vector Offset
256 Bytes Vector Table
Figure 39.
INT0 Mode 2 Vector Acquisition
During the INT0 Mode 2 acknowledge cycle, the low-order 8 bits of the vector is fetched from the data bus at the rising edge of T3 and the CPU acquires the 16-bit vector. Next, the PC is stacked. Finally, the 16-bit restart address is fetched from the vector table and execution begins at that address. Note: External vector acquisition is indicated by both MI and IORQ LOW. Two Wait States (TW) are automatically inserted for external vector fetch cycles. During RESET the Interrupt Vector Register (I) is initialized to 00H and, if necessary, should be set to a different value prior to the occurrence of a Mode 2 INT0 interrupt. Figure illustrates INT0 interrupt Mode 2 Timing.
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Last MC Vector Lower Address Read T1 T2 TW* TW* T3 Ti
INT0 Acknowledge Cycle Interrupt Manipulation Cycle T1 T2
Op Code Fetch Cycle
PC is pushed onto stack T1 T2 T3 T1
T2 T3 T1 T2 T3
T1
T2 T3
Phi INT0
Starting address
A0-A19 M1 MREQ IORQ RD WR
PC
SP-1
SP-2
Vector
Vector+1
Lower Vector
Starting Address (Lower Address) PCH PCL
Starting Address (Upper Address)
D0-D7 ST
*Two Wait States are automatically inserted
Figure 40.
INT0 Interrupt Mode 2 Timing Diagram
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode similar to INT0 Mode 2. The difference is that INT1 and INT2 generate the low-order byte of vector table address using the IL (Interrupt Vector Low) register rather than fetching it from the data bus. This difference is
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also the interrupt response sequence used for all internal interrupts (except TRAP). As depicted in Figure 41, the low-order byte of the vector table address has the most significant three bits of the software programmable IL register while the least significant five bits are a unique fixed value for each interrupt (INT1, INT2 and internal) source:
Memory 16-bit Vector I IL Fixed Code (5 bits) Vector + 1 Vector High-order 8 bits of starting address Low-order 8 bits of starting address 32 Bytes Vector Table
Figure 41.
INT1, INT2 Vector Acquisition
INT1 and INT2 are globally masked by IEF1 is 0. Each is also individually maskable by respectively clearing the ITE1 and ITE2 (bits 1,2) of the INT/TRAP control register to 0. During RESET, IEF1, ITE1 and ITE2 bits are reset to 0. Internal Interrupts Internal interrupts (except TRAP) use the same vectored response mode as INT1 and INT2. Internal interrupts are globally masked by IEF1 is 0. Individual internal interrupts are enabled/disabled by programming each
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individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of INT1 INT2 and internal interrupt are summarized in Table 9.
Table 9. Vector Table IL Interrupt Source INT1 INT2 PRT channel 0 PRT channel 1 DMA channel 0 DMA channel 1 CSI/O ASCI channel 0 ASCI channel 1 Priority H igh e s t b7 -- -- -- -- -- -- -- L est -- ow -- b6 -- -- -- -- -- -- -- -- -- b5 -- -- -- -- -- -- -- -- -- Fixed Code b4 0 0 0 0 0 0 0 0 1 b3 0 0 0 0 1 1 1 1 0 b2 0 0 1 1 0 0 1 1 0 b1 0 1 0 1 0 1 0 1 0 b0 0 0 0 0 0 0 0 0 0
Interrupt Acknowledge Cycle Timings
Figure 43 illustrates INT1, INT2, and internal interrupts timing. INT1 and INT2 are sampled at the falling edge of the clock state prior to T2 or T1 in the last machine cycle. If INT1 or INT2 is asserted Low at the falling edge of clock state prior to T3 or T1 in the last machine cycle, the interrupt request is accepted.
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Interrupt Sources During RESET
Interrupt Vector Register (I) All bits are reset to 0. Because I = 0 locates the vector tables starting at logical address 0000H vectored interrupts (INT0 Mode 2, INT1, INT2, and internal interrupts) overlap with fixed restart interrupts like RESET (0), NMI (0066H), INT0 Mode 1 (0038H) and RST (0000H-0038H). The vector table(s) are built elsewhere in memory and located on 256 byte boundaries by reprogramming I with the LD I, A instruction. IL Register Bits 7 - 5 are reset to 0 The IL Register can be programmed to locate the vector table for INT1, INT2 and internal interrupts on 32-byte subboundaries within the 256 byte area specified by I. IEF1, IEF2 Flags Reset to 0. Interrupts other than NMI and TRAP are disabled. ITC Register ITE0 set to 1. ITE1, ITE2 reset to 0. INT0 can be enabled by the EI instruction, which sets IEF1 to 1. Enabling INT1 and INT2 also requires that the ITE1 and ITE2 bits be respectively set to 1 by writing to ITC. I/O Control Registers Interrupt enable bits reset to 0. All Z8X180 on-chip I/O (PRT, DMAC, CSI/O, ASCI) interrupts are disabled and can be individually enabled by writing to each I/O control register interrupt enable bit.
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Return from Subroutine (RETI) Instruction Sequence
When the EDH/4DH sequence is fetched by the Z8X180, it is recognized as the RETI instruction sequence. The Z8X180 then refetches the RETI instruction with four T-states in the EDH cycle allowing the Z80 peripherals time to decode that cycle (See Figure 42). This procedure allows the internal interrupt structure of the peripheral to properly decode the instruction and behave accordingly. The M1E bit of the Operation Mode Control Register (OMCR) must be set to 0 so that M1 signal is active only during the refetch of the RETI instruction sequence. This condition is the desired operation when Z80 peripherals are connected to the Z8018X.
T1 T2 T3 T1 T2 T3 Ti Ti Ti T1 T2 T3 Ti T1 T2 T3 T1
Phi A0-A18 (A19) D0-D7 M1 (M1E = 1) M1 (M1E = 0) MREQ
PC EDH 4DH PC + 1 PC EDH PC + 1 4DH
RD ST Note: RETI machine cycles 9 and 10 not shown.
Figure 42.
RETI Instruction Sequence
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10 lists the conditions of all the control signals during this sequence for the
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Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts timing.
Table 10. RETI Control Signal States MI Machine Cycle States Address Data 1 2 3 4 5 6 7 8 9 10 T1-T3 1st EDH Op Code TI-T3 2nd 4DH Op Code T1 T1 T1 Don't Care Don't Care Don't Care 3-state 3-state 3-state RD WR MREQ IORQ 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 M1E=1 M1E=0 HALT ST 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
T1-T3 1st EDH Op Code T1 Don't Care 3-state
T1-T3 2nd 4DH Op Code T1-T3 SP T1-T3 SP+1 data data
IOC affects the IORQ/RD signals. M1E affects the assertion of M1. One state also reflects a 1 while the other reflects a 0
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INT1, INT2, internal interrupt acknowledge cycle PC Stacking T1 T2 TW*TW* T3 Ti Vector Table Read
Op Code fetch cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 Starting Address
Phi INT1,2 A0-A19 M1 MREQ IORQ RD WR D0-D7 ST MC: Machine Cycle * Two Wait States are automatically inserted. PCH PCL Starting address (L) Starting address (H) PC SP-1 SP-2 Vector Vector+1
Figure 43.
INT1, INT2 and Internal Interrupts Timing Diagram
Dynamic RAM Refresh Control
The Z8X180 incorporates a dynamic RAM refresh control circuit including 8-bit refresh address generation and programmable refresh timing. This circuit generates asynchronous refresh cycles inserted at the programmable interval independent of CPU program execution. For systems which do not use dynamic RAM, the refresh function can be disabled. When the internal refresh controller determines that a refresh cycle should occur, the current instruction is interrupted at the first breakpoint between machine cycles. The refresh cycle is inserted by placing the refresh address on A0-A7 and the RFSH output is driven Low.
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Refresh cycles may be programmed to be either two or three clock cycles in duration by programming the REFW (Refresh Wait) bit in the Refresh Control Register (RCR). The external WAIT input and the internal Wait State generator are not effective during refresh. Figure 44 depicts the timing of a refresh cycle with a refresh wait (TRW) cycle.
MCi
TR1
Refresh cycle
TRW* TR2
MCi+1
Refresh signal (Internal signal) Refresh address MREQ RFSH NOTE: * If three refresh cycles are specified, TRW is inserted. Otherwise, TRW is not inserted MC: Machine Cycle
A0 -- A7
Figure 44.
Refresh Cycle Timing Diagram
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Refresh Control Register (RCR) The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. Refresh Control Register (RCR: 36H)
Bit Bit/Field R/W Reset 7 REFE R/W 1 6 REFW R/W 1 5 4 ? ? ? 3 2 1 CYC1 R/W 0 0 CYC0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W REFE R/W
Value 0 1
Description REFE: Refresh Enable Disables the refresh controller Enables refresh cycle insertion. Refresh Wait (bit 6) Causes the refresh cycle to be two clocks in duration. Causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (TRW). Cycle Interval -- CYC1 and CYC0 specify the interval (in clock cycles) between refresh cycles. In the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the required refresh interval is less than or equal to 15.625 s. Thus, the underlined values indicate the best refresh interval depending on CPU clock frequency. CYC0 and CYC1 are cleared to 0 during RESET. Refer to Table 11.
6
REFW
R/W 0 1
1-0
CYC1-0 R/W
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Table 11. Insertion Interval 10 states 20 states 40 states 80 states
DRAM Refresh Intervals Time Interval
CYC1 0 0 1 1
CYC0 0 1 0 1
10 MHz (1.0 s)* (2.0 s)* (4.0 s)* (8.0 s)*
8 MHz (1.25 s)* (2.5 s)* (5.0 s)* (10.0 s)*
6 MHz 1.66 s 3.3 s 6.8 s 13.3 s
4 MHz 2.5 s 5.0 s 10.0 s 20.0 s
2.5 MHz 4.0 s 8.0 s 16.0 s 32.0 s
* Calculated interval
Refresh Control And RESET After RESET, based on the initialized value of RCR, refresh cycles occur with an interval of ten clock cycles and are three clock cycles in duration. Dynamic Ram Refresh Operation Notes 1. Refresh Cycle insertion is stopped when the CPU is in the following states: - - - - During RESET When the bus is released in response to BUSREQ During SLEEP mode During Wait States
2. Refresh cycles are suppressed when the bus is released in response to BUSREQ. However, the refresh timer continues to operate. Thus, the time at which the first refresh cycle occurs after the Z8X180 reacquires the bus depends on the refresh timer and has no timing relationship with the bus exchange.
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3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during SLEEP mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited. After this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and has no timing relationship with the exit from SLEEP mode. 4. Regarding (2) and (3), the refresh address is incremented by one for each successful refresh cycle, not for each refresh request. Thus, independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles.
DMA Controller (DMAC)
The Z8X180 contains a two-channel DMA (Direct Memory Access) controller which supports high speed data transfer. Both channels (channel 0 and channel 1) feature the following capabilities:
*
Memory Address Space Memory source and destination addresses can be directly specified anywhere within the 1024KB physical address space using 20-bit source and destination memory addresses. In addition, memory transfers can arbitrarily cross 64KB physical address boundaries without CPU intervention.
*
I/O Address Space I/O source and destination addresses can be directly specified anywhere within the 64KB I/O address space (16-bit source and destination I/O addresses).
*
Transfer Length Up to 64KB are transferred based on a 16- bit byte count register.
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*
DREQ Input Level- and edge-sense DREQ input detection are selectable. TEND Output Used to indicate DMA completion to external devices.
*
Transfer Rate Each byte transfer occurs every 6 clock cycles. Wait States can be inserted in DMA cycles for slow memory or I/O devices. At the system clock ( = 6 MHz, the DMA transfer rate is as high as 1.0 ) megabytes/second (no Wait States).
There is an additional feature disc for DMA interrupt request by DMA END. Each channel has the following additional specific capabilities: Channel 0
* * * * * * * * *
Memory to memory Memory to I/O Memory to memory mapped I/O transfers. Memory address increment, decrement, no-change Burst or cycle steal memory to/from memory transfers DMA to/from both ASCI channels Higher priority than DMAC channel 1
Channel 1 Memory to/from I/O transfer Memory address increment, decrement
DMAC Registers Each channel of the DMAC (channel 0, 1) contains three registers specifically associated with that channel.
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Channel 0
* * * * * * * * *
SAR0-Source Address Register DAR0-Destination Address Register BCR0-Byte Count Register
Channel 1 MAR1-Memory Address Register IAR1-I/O Address Register BCR1-Byte Count Register
The two channels share the following three additional registers in common: DSTAT-DMA Status Register DMODE-DMA Mode Register DCNTL-DMA Control Register
DMAC Block Diagram Figure 45 depicts the Z8X180 DMAC Block Diagram.
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Internal Address/Data Bus
DMA Source Address Register ch0 : SAR0 (20) DMA Destination Address Register ch0 : DAR0 (20) DMA Byte Count Register ch0 : BCR0 (16) DMA Destination Address Register ch1 : MAR1 (20) DMA I/O Address Register ch1 : IAR1 (16) DMA Byte Count Register ch1 : BCR1 (16)
DMA Status Register : DSTAT (8) DMA Mode Register : DMODE (8) DMA/WAIT Control Register : DCNTL (8)
Priority & Request Control
DREQ0 DREQ1
DMA Control
Bus & CPU Control
TEND0 Incrementer/Decrementer (16) TEND1 Interrupt Request
Figure 45.
DMAC Block Diagram
DMAC Register Description
DMA Source Address Register Channel 0 (SAR0 I/O Address = 20H to 22H) Specifies the physical source address for channel 0 transfers. The register contains 20 bits and can specify up to 1024KB memory addresses or up to 64KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O.
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DMA Destination Address Register Channel 0 (DAR0 I/O Address = 23H to 25H) Specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024KB memory addresses or up to 64KB I/O addresses. Channel 0 destination can be memory, I/O, or memory mapped I/O. DMA Byte Count Register Channel 0 (BCR0 I/O Address = 26H to 27H) Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64KB transfers. When one byte is transferred, the register is decremented by one. If n bytes are transferred, n is stored before the DMA operation. DMA Memory Address Register Channel 1 (MAR1: I/O Address = 28H to 2AH) Specifies the physical memory address for channel 1 transfers. This address may be a destination or source memory address. The register contains 20 bits and may specify up to 1024KB memory address. DMA I/O Address Register Channel 1 (IAR1: I/O Address = 2BH to 2CH) Specifies the I/O address for channel 1 transfers. This address may be a destination or source I/O address. The register contains 16 bits and may specify up to 64KB I/O addresses. DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to 2FH) Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64KB transfers. When one byte is transferred, the register is decremented by one.
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DMA Status Register (DSTAT) DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT also determines DMA transfer status, that is, completed or in progress. DMA Status Register (DSTAT: 30H)
Bit Bit/Field R/W Reset 7 DE1 R/W 0 6 DE0 R/W 0 5 DWE1 W 1 4 DWE0 W 1 3 DIE1 R/W 0 2 DIE0 R/W 0 1 ? ? ? 0 DME R
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W DE1 R/W
Value
Description Enable Channel 1 -- When DE1 = 1 and DME = 1, channel 1 DMA is enabled. When a DMA transfer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC. When DE1 = 0 and the DMA interrupt is enabled (DIE1 = 1), a DMA interrupt request is made to the CPU. To perform a software write to DE1, DWE1 is written with 0 during the same register write access. Writing DE1 to 0 disables channel 1 DMA, but DMA is restartable. Writing DE1 to 1 enables channel 1 DMA and automatically sets DME (DMA Main Enable) to 1. DE1 is cleared to 0 during RESET.
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Bit Position 6
Bit/Field R/W DE0 R/W
Value
Description Enable Channel 0 -- When DE0 = 1 and DME = 1, channel 0 DMA is enabled. When a DMA transfer terminates BCR0 = 0), DE0: is reset to 0 by the DMAC. When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is made to the CPU. To perform a software write to DE0, DWE0 must be written with 0 during the same register write access. Writing DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel 0 DMA and automatically sets DME (DMA Main Enable) to 1. DE0 is cleared to 0 during RESET. Bit Write Enable 1 -- When performing any software write to DEI, DWE1 must be written with 0 during the same access. DWE1 write value of 0 is not held and DWE1 is always read as 1. Bit Write Enable 0 -- When performing any software write to DE0, DWE0 must be written with 0 during the same access. DWE0 write value of 0 is not held and DWE0 is always read as 1. DMA Interrupt Enable Channel 1 -- When DIE1 is set to 1, the termination channel 1 DMA transfer (indicated when DE1 is 0) causes a CPU interrupt request to be generated. When DIE1 is 0, the channel 1 DMA termination interrupt is disabled. DIE1 is cleared to 0 during RESET. DMA Interrupt Enable Channel 0 -- When DIE0 is set to 1, the termination channel 0 of DMA transfer (indicated when DE0 is 0) causes a CPU interrupt request to be generated. When DIE0 is 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET.
5
DWE1
W
4
DWE0
W
3
DIE1
R/W
2
DIE0
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Bit Position 0
Bit/Field R/W DME R
Value
Description DMA Main Enable -- A DMA operation is only enabled when its DE bit DE0 for channel 0, DE1 for channel 1) and the DME bit are set to 1.
When NMI occurs, DME is reset to 0, thus disabling DMA activity during the NMI interrupt service routine. To restart DMA, DE0 and/or DE1 must be written with 1 (even if the contents are already 1). This action automatically sets DME to 1, allowing DMA operations to continue. DME cannot be directly written. It is cleared to 0 by NMI or indirectly set to 1 by setting DE0 and/or DE1 to 1.DME is cleared to 0 during RESET.
DMA Mode Register (DMODE) DMODE is used to set the addressing and transfer mode for channel 0. DMA Mode Register (DMODE: 31H)
Bit Bit/Field R/W Reset 7 ? ? ? 6 5 DM1 R/W 0 4 DM0 R/W 0 3 SM1 R/W 0 2 SM0 R/W 0 1 MMOD R/W 0 0 ? ? ?
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 5-4
Bit/Field R/W DM1:0 R/W
Value
Description Destination Mode Channel 0 -- Specifies whether the destination for channel 0 transfers is memory, I/O or memory mapped I/O and the corresponding address modifier. Reference Table 12.
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Bit Position 3-2
Bit/Field R/W SM1:0 W
Value
Description Source Mode Channel -- Specifies whether the source for channel 0 transfers is memory, I/O, or memory mapped I/O and the corresponding address modifier. Reference Table 13. DMA Memory Mode Channel 0 -- When channel 0 is configured for memory to/from memory transfers, the external DREQ0 input is not used to control the transfer timing. Instead, two automatic transfer timing modes are selectable - BURST (MMOD is 1) and CYCLE STEAL (MMOD is 0). For BURST memory to/from memory transfers, the DMAC takes control of the bus continuously until the DMA transfer completes (as shown by the byte count register is 0). In CYCLE STEAL mode, the CPU is given a cycle for each DMA byte transfer cycle until the transfer is completed. For channel 0 DMA with I/O source or destination, the DREQ0 input times the transfer and thus MMOD is ignored.
1
MMOD
R/W
Table 12. DM1 0 0 1 1
Channel 0 Destination Memory/I/O Memory Memory Memory I/O Address Increment/Decrement +1 -1 fixed fixed
DM0 0 1 0 1
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Table 13. SM1 0 0 1 1
Channel 0 Source Memory/I/O Memory Memory Memory I/O Address lncrement/Decrement +1 -1 fixed fixed
SM0 0 1 0 1
Table 14 describes all DMA TRANSFER mode combinations of DM0 DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented, 12 combinations are available.
Table 14. Transfer Mode Combinations Increment/Decrement SAR0+1, DAR0+1 SAR0-1, DAR0+1 SAR0 fixed, DAR0+ 1 SAR0 fixed DAR0+1 SAR0+1, DAR0-1 SAR0-1,DAR0-1 SAR0 fixed, DAR0-1 SAR0 fixed. DAR0-1 SAR0+ 1, DAR0 fixed SAR0-1, DAR0 fixed
DM1 DM0 SM1 SM0 Transfer Mode 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Memory to Memory Memory to Memory Memory* to Memory I/O to Memory Memory to Memory Memory to Memory Memory to Memory I/O to Memory Memory to Memory* Memory to Memory* Reserved Reserved
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Table 14.
Transfer Mode Combinations Increment/Decrement SAR0+1, DAR0 fixed SAR0-1, DAR0 fixed
DM1 DM0 SM1 SM0 Transfer Mode 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Memory to I/O Memory to I/O Reserved Reserved
Note: *: includes memory mapped I/O.
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of Wait States into DMAC (and CPU) accesses of memory or I/O Also, the DMA request mode for each DREQ DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL also sets the DMA transfer mode for channel 1, which is limited to memory to/from I/O transfers.
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DMA/WAIT Control Register (DCNTL: 32H)
Bit Bit/Field R/W Reset 7 MWI1 R/W 0 6 MWI0 R/W 0 5 IWI1 R/W 0 4 IWI0 R/W 0 3 DMS1 R/W 0 2 DMS0 R/W 0 1 DIM1 R/W 0 0 DIM0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7-6
Bit/Field R/W MWI1-0 R/W
Value
Description Memory Wait Insertion -- Specifies the number of wait states introduced into CPU or DMAC memory access cycles. MWI1 and MWI0 are set to 1 during RESET. See section on Wait State Generator for details. Wait Insertion -- Specifies the number of Wait States introduced into CPU or DMAC I/O access cycles. IWI1 and IWI0 are set to 1 during RESET. See section on Wait State Generator for details. DMA Request Sense -- Specifies the DMA request sense for channel 0 (DREQ0) and channel 1 (DREQ1) respectively. When reset to 0, the input is level-sense. When set to 1, the input is edge-sense. DMA Channel 1 I/O and Memory Mode -- Specifies the source/destination and address modifier for channel 1 memory to/from I/O transfer modes. Reference Table 15.
5-4
IWI1-0
R/W
3-2
DMS1-0 R/W
1-0
DIM1-0
R/W
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Table 15. DIM1 0 0 1 1
Channel 1 Transfer Mode Transfer Mode Memory to I/O Memory to I/O I/O to Memory I/O to Memory Address Increment/Decrement MARI +1, IAR1 fixed MARI -1, IAR1 fixed IAR1 fixed, MAR1+1 IAR1 fixed, MAR1-1
DIM0 0 1 0 1
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
Bit Bit/Field R/W Reset R/W 0 R/W 0 7 6 5 4 Reserved R/W 0 R/W 0 R/W 0 3 2 1 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field
R/W R/W
Value Description 0 1 Alternating Channels DMA Channels are independent Toggle between DMA channels for same device Currently selected DMA channel when Bit 7 = 1 0 0 1 Reserved. Must be 0. TOUT/DREQ is DREQ In TOUT/DREQ is TOUT Out
6 5-4 3 Reserved
R/W R/W R/W
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Bit Position 2-0
Bit/Field
R/W R/W
Value Description 000 001 010 011 111 DMA1 ext TOUT/DREQ DMA1 ASCI0 DMA1 ASCI1 DMA1 ESCC DMA1 PIA27-20 (P1284)
DMA Register Description Bit 7
This bit must be set to 1 only when both DMA channels are set to take their requests from the same device. If this bit is 1 (it resets to 0), the TEND output of DMA channel o sets a flip-flop, so that thereafter the device' request is visible to channel 1, but not visible to channel 0. The s internal TEND signal of channel 1 clears the FF, so that thereafter, the device' request is visible to channel 0, but no visible to channel 1. s If DMA request are from differing sources, DMA channel 0 request is forced onto DMA channel 1 after TEND output of DMA channel 0 sets the flop-flop to alternate.
Bit 6
When both DMA channels are programmed to take their requests from the same device, this bit (FF mentioned in the previous paragraph) controls which channel the device' request is presented to: 0 = DMA0, 1 s = DMA l. When Bit 7 is 1, this bit is automatically toggled by the channel end output of the channels.
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Bits 5-3
Reserved. Must be 0.
Bits 2-0
With DIM1, bit 1 of DCNTL, these bits control which request is presented to DMA channel 1, as described below:
DIM1 0 0 0 0 0 0 0 1 1 1 1 1 1 1
IAR18-16 Request Routed to DMA Channel 1 000 001 010 011 10X 1X0 111 000 001 010 011 10X 1X0 111 DREQ1 ASCI0 Tx ASCI1 Tx ext CKA0/DREQ0 Reserved Reserved Reserved ext DREQ1 ASCI0 Rx ASCI1 Rx ext CKA0/DREQ0 Reserved Reserved Reserved
DMA Operation
This section discusses the three DMA operation modes for channel 0:
* * *
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Memory to/from memory Memory to/from I/O Memory to/from memory mapped I/O
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In addition, the operation of channel 0 DMA with the on-chip ASCI (Asynchronous Serial Communication Interface) as well as Channel 1 DMA are described.
Memory to Memory-- Channel 0
For memory to/from memory transfers, the external DREQ0 input is not used for DMA transfer timing. Rather, the DMA operation is timed in one of two programmable modes - BURST or CYCLE STEAL. In both modes, the DMA operation automatically proceeds until termination (shown by byte count-BCR0) = 0. In BURST mode, the DMA operation proceeds until termination. In this case, the CPU cannot perform any program execution until the DMA operation is completed. In CYCLE STEAL mode, the DMA and CPU operation are alternated after each DMA byte transfer until the DMA is completed. The sequence:
* *
1 CPU Machine Cycle DMA Byte Transfer
is repeated until DMA is completed. Figure 46 describes CYCLE STEAL mode DMA timing.
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DMA cycle
CPU cycle DMA cycle (transfer 1 byte)
CPU cycle
DMA cycle
T1 T2 T3 T1 T2 T3 T1
T2 T3 T1
T2 T3 T1 T2 LD g,m operand address
Phi
LD g,m Op Code address Source memory address Destination memory address
Address MREQ RD WR
m Read data Write data, m
Data
Figure 46.
DMA Timing Diagram-CYCLE STEAL Mode
To initiate memory to/from memory DMA transfer for channel 0, perform the following operations. 1. Load the memory source and destination address into SAR0 and DAR0 2. Specify memory to/from memory mode and address increment/ decrement in the SM0 SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0. 4. Specify burst or cycle steal mode in the MMOD bit of DCNTL. 5. Program DE0 = 1 (with DWE0 = 0 in the same access) in DSTAT and the DMA operation starts one machine cycle later. If interrupt occurs at the same time, the DIE0 bit must be set to 1.
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Memory to I/O (Memory Mapped I/O) -- Channel 0
For memory to/from I/O (and memory to/from memory mapped I/O) the DREQ0 input is used to time the DMA transfers. In addition, the TEND0 (Transfer End) output is used to indicate the last (byte count register BCR0 = 00H) transfer. The DREQ0 input can be programmed as level- or edge-sensitive. When level-sense is programmed, the DMA operation begins when DREQ0 is sampled Low. If DREQ0 is sampled High, after the next DMA byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in Figure 47, DREQ0 is sampled at the rising edge of the clock cycle prior to T3, (that is, either T2 or Tw).
DMA Write Cycle
Tw Tw T3 T1
CPU Machine Cycle
T2 T3 T1
DMA Read Cycle
T2 T3 T1
DMA Write Cycle (I/O)
T2 Tw Tw T3 T1 T2
Phi ** DREQ0 ** DREQ0 is sampled at ** **
Figure 47.
CPU Operation and DMA Operation DREQ0 is Programmed for Level-Sense
When edge-sense is programmed, DMA operation begins at the falling edge of DREQ0 If another falling edge is detected before the rising edge of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the DMAC continues operating. If an edge is not detected, the CPU is given control after the current byte DMA transfer completes. The CPU continues operating until a DREQ0 falling edge is detected before the
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rising edge of the clock prior to T3 at which time the DMA operation (re)starts. Figure 48 depicts the edge-sense DMA timing.
DMA Write Cycle
Tw T3 T1
CPU Machine Cycle
T2 T3 T1
DMA Read Cycle
T2 T3
DMA Write Cycle
T1 T2 Tw T3 T1
CPU Machine Cycle
T2 T3
Phi
** ** ** **
DREQ0 ** DREQ0 is sampled at
Figure 48.
CPU Operation and DMA Operation DREQ0 is Programmed for Edge-Sense
During the transfers for channel 0, the TEND0 output goes Low synchronous with the write cycle of the last (BCR0 = OOH) DMA transfer (Reference Figure 49).
Last DMA cycle (BCR0 = 00H) DMA read cycle
T1 T2 T3 T1
DMA write cycle
T2 TW T3
Phi
TEND0
Figure 49.
TEND0 Output Timing Diagram
The DREQ0 and TEND0 pins are programmably multiplexed with the CKA0 and CKA1 ASCI clock input/outputs. However, when DMA channel 0 is programmed for memory to/from I/O (and memory to/from
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memory mapped I/O. transfers, the CKA0/ DREQ0 pin automatically functions as input pin or output pin even if it has been programmed as output pin for CKA0. And the CKA1/ TEND0 pin functions as an input or an output pin for TEND0 by setting CKA1D to 1 in CNTLA1. To initiate memory to/from I/O (and memory to/from memory mapped I/O) DMA transfer for channel 0, perform the following operations: 1. Load the memory and I/O or memory mapped I/O source and destination addresses into SAR0 and DAR0. I/O addresses (not memory mapped I/O are limited to 16 bits (A0- A15). Make sure that bits A16, A17 and A19 are 0 (A18 is a don't care) to correctly enable the external DREQ0 input. 2. Specify memory to/from I/O or memory to/from memory mapped I/O mode and address increment/decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0. 4. Specify whether DREQ0 is edge- or level-sense by programming the DMS0 bit of DCNTL. 5. Enable or disable DMA termination interrupt with the DIE0 bit in DSTAT. 6. Program DE0: = 1 (with DWEO = 0 in the same access) in DSTAT and the DMA operation begins under the control of the DREQ0 input.
Memory to ASCI - Channel 0
Channel 0 has extra capability to support DMA transfer to/from the onchip two channel ASCI. In this case, the external DREQ0 input is not used for DMA timing. Rather, the ASCI status bits are used to generate an internal DREQ0 The TDRE (Transmit Data Register Empty) bit and the RDRF (Receive Data Register Full) bit are used to generate an internal
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DREQ0 for ASCI transmission and reception respectively. To initiate memory to/from ASCI DMA transfer, perform the following operations: 1. Load the source and destination addresses into SAR0 and DAR0 Specify the I/O (ASCI) address as follows: a. Bits A0-A7 must contain the address of the ASCI channel transmitter or receiver (I/O addresses 6H-9H). b. Bits A8-A15 must equal 0. c. Bits SAR17-SAR16 must be set according to Table 16 to enable use of the appropriate ASCI status bit as an internal DMA request.
Table 16. SAR18 X X X X DMA Transfer Request SAR17 0 0 1 1 SAR16 DMA Transfer Request 0 1 0 1
DREQ0
RDRF (ASCI channel 0) RDRF (ASCI channel 1) Reserved
Note: X = Don' care t
DAR18 X X X X
DAR17 0 0 1 1
DAR16 DMA Transfer Request 0 1 0 1
DREQ0
TDRE (ASCI channel O) TDRE (ASCI channel 1) Reserved
Note: X = Don' care t
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2. Specify memory I/O transfer mode and address increment/ decrement in the SM0, SM1, DM0 and DM1 bits of DMODE. 3. Load the number of bytes to transfer in BCR0 4. The DMA request sense mode (DMS0 bit in DCNTL) must be specified as edge sense. 5. Enable or disable DMA termination interrupt with the DIE0 bit in DSTAT. 6. Program DE0 =1 (with DWE0 = 0 in the same access) in DSTAT and the DMA operation with the ASCI begins under control of the ASCI generated internal DMA request. The ASCI receiver or transmitter using DMA is initialized to allow the first DMA transfer to begin. The ASCI receiver must be empty as shown by RDRF = 0. The ASCI transmitter must be full as shown by TDRE = 0. Thus, the first byte is written to the ASCI Transmit Data Register under program control. The remaining bytes are transferred using DMA. Channel 1 DMA DMAC Channel 1 performs memory to/from I/O transfers. Except for different registers and status/control bits, operation is exactly the same as described for channel 0 memory to/from I/O DMA. To initiate a DMA channel 1 memory to/from I/O transfer, perform the following operations: 1. Load the memory address (20 bits) into MAR1. 2. Load the I/O address (16 bits) into IAR1. 3. Program the source/destination and address increment/decrement mode using the DIM1 and DIM0 bits in DCNTL.
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4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in DCNTL. 5. Enable or disable DMA termination interrupt with the DIE1 bit in DSTAT. 6. Program DE1 = 1 (with DWE1 = 0 in the same access) in DSTAT and the DMA operation with the external I/O device begins using the external DREQ1 input and TEND1 output. DMA Bus Timing When memory (and memory mapped I/O) is specified as a source or destination, MREQ goes Low during the memory access. When I/O is specified as a source or destination, IORQ goes Low during the I/O access. When I/O (and memory mapped I/O) is specified as a source or destination, the DMA timing is controlled by the external DREQ input and the TEND output indicates DMA termination Note: External I/O devices may not overlap addresses with internal I/O and control registers, even using DMA. For I/O accesses, one Wait State is automatically inserted. Additional Wait States can be inserted by programming the on-chip wait state generator or using the external WAIT input. Note: For memory mapped I/O accesses, this automatic I/O Wait State is not inserted. For memory to memory transfers (channel 0 only), the external DREQ0 input is ignored. Automatic DMA timing is programmed as either BURST or CYCLE STEAL. When a DMA memory address carry/borrow between bits A15 and A16 of the address bus occurs (crossing 64KB boundaries), the minimum bus
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cycle is extended to 4 clocks by automatic insertion of one internal Ti state. DMAC Channel Priority For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority over channel 1. When channel 0 is performing a memory to/from memory transfer, channel 1 cannot operate until the channel 0 operation has terminated. If channel 1 is operating, channel 0 cannot operate until channel 1 releases control of the bus. DMAC and BUSREQ, BUSACK The BUSREQ and BUSACK inputs allow another bus master to take control of the Z8X180 bus. BUSREQ and BUSACK take priority over the on-chip DMAC and suspends DMAC operation. The DMAC releases the bus to the external bus master at the breakpoint of the DMAC memory or I/O access. Since a single byte DMAC transfer requires a read and a write cycle, it is possible for the DMAC to be suspended after the DMAC read, but before the DMAC write. Hence, when the external master releases the Z8X180 bus (BUSREQ High), the on-chip DMAC correctly continues the suspended DMA operation.
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DMAC Internal Interrupts Figure 50 illustrates the internal DMA interrupt request generation circuit.
IEF1
DE1 DIE1
DMA ch1 Interrupt Request
DE0 DIE0
DMA ch0 Interrupt Request
Figure 50.
DMA Interrupt Request Generation
DE0 and DE1 are automatically cleared to 0 by the Z8X180 at the completion (byte count is 0) of a DMA operation for channel 0 and channel 1, respectively. They remain 0 until a 1 is written. Because DE0: and DE1 use level sense, an interrupt occurs if the CPU IEF1 flag is set to 1. Therefore, the DMA termination interrupt service routine disables further DMA interrupts (by programming the channel DIE bit is 0) before enabling CPU interrupts (for example, IEF1 is set to 1). After reloading the DMAC address and count registers, the DIE bit can be set to 1 to reenable the channel interrupt, and at the same time DMA can resume by programming the channel DE bit = 1. DMAC and NMI NMI, unlike all other interrupts, automatically disables DMAC operation by clearing the DME bit of DSTAT. Thus, the NMI interrupt service routine responds to time-critical events without delay due to DMAC bus usage. Also, NMI can be effectively used as an external DMA abort input, recognizing that both channels are suspended by the clearing of DME.
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If the falling edge of NMI occurs before the falling clock of the state prior to T3 (T2 or Tw) of the DMA write cycle, the DMAC is suspended and the CPU starts the NMI response at the end of the current cycle. By setting a channel's DE bit to 1, the channel's operation is restarted and DMA correctly resumes from its suspended point by NMI. (Reference Figure 51.)
DMA read cycle
T1 T2 T3
DMA write cycle
T1 T2 T3
NMI acknowledge cycle
T1
Phi
NMI DME = " (DMA Stop) 0"
Figure 51.
NMI and DMA Operation Timing Diagram
DMAC and RESET During RESET the bits in DSTAT, DMODE, and DCNTL are initialized as stated in their individual register descriptions. Any DMA operation in progress is stopped, allowing the CPU to use the bus to perform the RESET sequence. However, the address register (SAR0, DAR0 MAR1, IAR1) and byte count register (BCR0 BCR1) contents are not changed during RESET.
Asynchronous Serial Communication Interface (ASCI)
The Z8X180 on-chip ASCI has two independent full-duplex channels. Based on full programmability of the following functions, the ASCI directly communicates with a wide variety of standard UARTs (Universal Asynchronous Receiver/Transmitter) including the Z8440 SIO and the Z85C30 SCC.
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The key functions for ASCI on Z80180, Z8S180 and Z8L180 class processors are listed below. Each channel is independently programmable.
* * * * * * * * * *
Full-duplex communication 7- or 8-bit data length Program controlled 9th data bit for multiprocessor communication 1 or 2 stop bits Odd, even, no parity Parity, overrun, framing error detection Programmable baud rate generator, /16 and /64 modes Modem control signals - Channel 0 contains DCD0, CTS0 and RTS0; Channel 1 contains CTS1 Programmable interrupt condition enable and disable Operation with on-chip DMAC
ASCI Block Diagram for the Z8S180/Z8L180-Class Processors
Figure 52 illustrates the ASCI block diagram.
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Internal Address/Data Bus Interrupt Request
ASCI Transmit Data Register ch 0 : TDR0 TXA0 ASCI Transmit Shift Register* ch 0 : TSR0 ASCI Receive Data Register ch 0 : RDR0 RXA0 ASCI Receive Shift Register* ch 0 : RSR0 (8) ASCI Control Register A ch 0 : CNTLA0 (8) ASCI Control Register B ch 0 : CNTLB0 (8) ASCI Status Register ch 0 : STAT0 (8) ASCI Control
ASCI Transmit Data Register ch 1 : TDR1 ASCI Transmit Shift Register* ch 1 : TSR1 ASCI Receive Data Register ch 1 : RDR1 ASCI Receive Shift Register* ch 1 : RSR1 (8) ASCI Control Register A ch 1 : CNTLA1 (8) ASCI Control Register B ch 1 : CNTLB1 (8) ASCI Status Register ch 1 : STAT1 (8) CTS1 RXA1 TXA1
RTS0 CTS0 DCD0
CKA0 CKA1
Baud Rate Generator 0 Baud Rate Generator 1
Phi * Not program Accessible
Figure 52.
ASCI Block Diagram
ASCI Register Description
The following subparagraphs explain the various functions of the ASCI registers. ASCI Transmit Shift Register 0, 1 (TSR0, 1) When the ASCI Transmit Shift Register receives data from the ASCI Transmit Data Register (TDR), the data is shifted out to the TXA pin.
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When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR idles by outputting a continuous High level. The TSR is not program-accessible. ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H) Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out the previous byte of data. Thus, the ASCI transmitter is double buffered. Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this read operation. ASCI Transmit Data Register Ch. 0 (TDR0: 06H)
Bit Bit/Field R/W Reset 7 6 5 4 3 R/W 0 2 1 0 ASCI Transmit Channel 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI Transmit Data Register Ch. 1 (TDR1: 07H)
Bit Bit/Field R/W Reset 7 6 5 4 3 R/W 0 2 1 0 ASCI Transmit Channel 1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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ASCI Receive Shift Register 0,1(RSR0, 1) This register receives data shifted in on the RXA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. The RSR is not program-accessible. ASCI Receive Data Register 0,1 (RDR0, 1: I/O Address = 08H, 09H) When a complete incoming data byte is assembled in RSR, it is automatically transferred to the RDR if RDR is empty. The next incoming data byte can be shifted into RSR while RDR contains the previous received data byte. Thus, the ASCI receiver on Z80180 is doublebuffered. ASCI Receive Data Register Ch. 0 (RDR0: 08H)
Bit Bit/Field R/W Reset 7 6 5 4 3 R/W 0 2 1 0 ASCI Receive Channel 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI Receive Data Register Ch. 1 (RDR1: 09H)
Bit Bit/Field R/W Reset 7 6 5 4 3 R/W 0 2 1 0 ASCI Receive Channel 1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
\
On the Z8S180 and Z8L180-class processors are quadruple buffered. The ASCI Receive Data Register is a read-only register. However, if RDRF =
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0, data can be written into the ASCII Receive Data Register, and the data
can be read. ASCI Status Register 0, 1 (STAT0, 1) Each channel status register allows interrogation of ASCI communication, error and modem control signal status, and enabling or disabling of ASCI interrupts. ASCI Status Register 0 (STAT0: 04H)
Bit Bit/Field R/W Reset 7 RDRF R 0 6 OVRN R 0 5 PE R 0 4 FE R 0 3 RIE R/W 0 2 DCD0 R 0 1 TDRE R 0 0 TIE R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W RDRF R
Value
Description Receive Data Register Full -- RDRF is set to 1 when an incoming data byte is loaded into RDR. If a framing or parity error occurs, RDRF remains set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR, when the DCD0 input is High, in IOSTOP mode, and during RESET. Overrun Error -- OVRN is set to 1 when RDR is full and RSR becomes full. OVRN is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.
6
OVRN
R
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Bit Position 5
Bit/Field R/W PE R
Value
Description Parity Error -- PE is set to 1 when a parity error is detected on an incoming data byte and ASCI parity detection is enabled (the MOD1 bit of CNTLA is set to 1). PE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. Framing Error -- If a receive data byte frame is delimited by an invalid stop bit (that is, 0, should be 1), FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. Receive Interrupt Enable -- RIE must be set to 1 to enable ASCI receive interrupt requests. When RIE is 1, if any of the flags RDRF, OVRN, PE, or FE become set to 1, an interrupt request is generated. For channel 0, an interrupt is also generated by the transition of the external DCD0 input from Low to High. Data Carrier Detect -- Channel 0 has an external DCD0 input pin. The DCD0 bit is set to 1 when the DCD0 input is HIGH. It is cleared to 0 on the first read of (STAT0, following the DCD0 input transition from HIGH to LOW and during RESET. When DCD0 is 1, receiver unit is reset and receiver operation is inhibited. Transmit Data Register Empty -- TDRE = 1 indicates that the TDR is empty and the next transmit data byte is written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. When the external CTS input is High, TDRE is reset to 0.
4
FE
R
3
RIE
R/W
2
DCD0
R
1
TDRE
R
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Bit Position 0
Bit/Field R/W TIE R/W
Value
Description Transmit Interrupt Enable -- TIE must be set to 1 to enable ASCI transmit interrupt requests. If TIE is 1, an interrupt is requested when TDRE is 1. TIE is cleared to 0 during RESET.
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ASCI Control Register A0, 1 (CNTLA0, 1)
Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode.
ASCI Status Register 1 (STAT1: 05H)
Bit Bit/Field R/W Reset 7 RDRF R 0 6 OVRN R 0 5 PE R 0 4 FE R 0 3 RIE R/W 0 2 CTS1E R/W 0 1 TDRE R 0 0 TIE R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W RDRF R
Value
Description Receive Data Register Full -- RDRF is set to 1 when an incoming data byte is loaded into RDR. Note that if a framing or parity error occurs, RDRF is still set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR, when the DCD0 input is High, in IOSTOP mode, and during RESET. Overrun Error -- OVRN is set to 1 when RDR is full and RSR becomes full. OVRN is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. Parity Error -- PE is set to 1 when a parity error is detected on an incoming data byte and ASCI parity detection is enabled (the MOD1 bit of CNTLA is set to 1). PE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET.
6
OVRN
R
5
PE
R
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Bit Position 4
Bit/Field R/W FE R
Value
Description Framing Error -- If a receive data byte frame is delimited by an invalid stop bit (that is, 0, should be 1), FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is High, in IOSTOP mode, and during RESET. Receive Interrupt Enable -- RIE must be set to 1 to enable ASCI receive interrupt requests. When RIE is 1, if any of the flags RDRF, OVRN, PE, or FE become set to 1, an interrupt request is generated. For channel 0, an interrupt is also generated by the transition of the external DCD0 input from Low to High. Channel 1 CTS Enable -- Channel 1 has an external CTS1 input which is multiplexed with the receive data pin (RXS) for the CSI/O (Clocked Serial I/O Port). Setting CTS1E to 1 selects the CTS1 function and clearing CTS1E to 0 selects the RXS function. Transmit Data Register Empty -- TDRE = 1 indicates that the TDR is empty and the next transmit data byte is written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. When the external CTS input is High, TDRE is reset to 0. Transmit Interrupt Enable -- TIE must be set to 1 to enable ASCI transmit interrupt requests. If TIE is 1, an interrupt is requested when TDRE is 1. TIE is cleared to 0 during RESET.
3
RIE
R/W
2
CTS1E
R/W
1
TDRE
R
0
TIE
R/W
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ASCI Control Register A0, 1 (CNTLA0, 1) Each ASCI channel Control Register A configures the major operating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Control Register A 0 (CNTLA0: 00H)
Bit Bit/Field R/W Reset 7 MPE R/W 0 6 RE R/W 0 5 TE R/W 0 4 RTS0 R/W 1 3 MPBR/ EFR R/W X 2 MOD2 R/W 0 1 MOD1 R/W 0 0 MOD0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W MPE R/W
Value
Description Multi-Processor Mode Enable -- The ASCI has a multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disables the wakeup feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) is 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB is 0) are ignored by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags.
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Bit Position 6
Bit/Field R/W RE R/W
Value
Description Receiver Enable -- When RE is set to 1, the ASCI receiver is enabled. When RE is reset to 0, the receiver is disabled and any receive operation in progress is interrupted. However, the RDRF and error flags are not reset and the previous contents of RDRF and error flags are held. RE is cleared to 0 in IOSTOP mode, and during RESET. Transmitter Enable -- When TE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode, and during RESET. Request to Send Channel 0 -- When RTS0 is reset to 0, the RTS0 output pin goes Low. When RTS0 is set to 1, the RTS0 output immediately goes High. Multiprocessor Bit Receive/Error Flag Reset -- When multiprocessor mode is enabled (MP in CNTLB is 1), MPBR, when read, contains the value of the MPB bit for the last receive operation. When written to 0, the EFR function is selected to reset all error flags (OVRN, FE and PE) to 0. MPBR/EFR is undefined during RESET.
5
TE
R/W
4
RTS0
R/W
3
MPBR/ EFR
R/W
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Bit Position 2-0
Bit/Field R/W MOD2-0 R/W
Value
Description ASCI Data Format Mode 2, 1, 0 -- These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled MOD0 0: 1 stop bit 1: 2 stop bits The data formats available based on all combinations of MOD2, MOD1 and MOD0 are described in Table 17.
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ASCI Control Register A 1 (CNTLA1: 01H)
Bit Bit/Field R/W Reset 7 MPE R/W 0 6 RE R/W 0 5 TE R/W 0 4 CKA1D R/W 0 3 MPBR/ EFR R/W X 2 MOD2 R/W 0 1 MOD1 R/W 0 0 MOD0 R/W 0
R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W MPE R/W
Value
Description Multi-Processor Mode Enable -- The ASCI has a multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disables the wakeup feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) is 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB = 0) are ignored by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags. Receiver Enable -- When RE is set to 1, the ASCI receiver is enabled. When RE is reset to 0, the receiver is disabled and any receive operation in progress is interrupted. However, the RDRF and error flags are not reset and the previous contents of RDRF and error flags are held. RE is cleared to 0 in IOSTOP mode, and during RESET.
6
RE
R/W
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Bit Position 5
Bit/Field R/W TE R/W
Value
Description Transmitter Enable -- When TE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode, and during RESET. CKA1 Clock Disable -- When CKA1D is set to 1, the multiplexed CKA1/TEND0 pin is used for the TEND0 function. When CKA1 D is 0, the pin is used as CKA1, an external data dock input/output for channel 1 Multiprocessor Bit Receive/Error Flag Reset -- When multiprocessor mode is enabled (MP in CNTLB is 1), MPBR, when read, contains the value of the MPB bit for the last receive operation. When written to 0, the EFR function is selected to reset all error flags (OVRN, FE and PE) to 0. MPBR/EFR is undefined during RESET.
4
CKA1D
R/W
3
MPBR/ EFR
R/W
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Bit Position 2-0
Bit/Field R/W MOD2-0 R/W
Value
Description ASCI Data Format Mode 2, 1, 0 -- These bits program the ASCI data format as follows. MOD2 0: 7 bit data 1: 8 bit data MOD1 0: No parity 1: Parity enabled MOD0 0: 1 stop bit 1: 2 stop bits The data formats available based on all combinations of MOD2, MOD1 and MOD0 are described in Table 17.
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Table 17. MOD2 0 0 0 0 1 1 1 1
Data Formats MOD1 0 0 1 1 0 0 1 1 MOD0 0 1 0 1 0 1 0 1 Data Format Start + 7 bit data + 1 stop Start + 7 bit date + 2 Stop Start + 7 bit data + parity + 1 stop Start + 7 bit data + parity + 2 stop Start + 8 bit data + 1 stop Start + 8 bit data + 2 stop Start + 8 bit data + parity + 1 stop Start + 8 bit date + parity + 2 stop
ASCI Control Register B0, 1 (CNTLB0, 1) Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection.
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ASCI Control Register B 0 (CNTLB0: 02H) ASCI Control Register B 1 (CNTLB1: 03H)
Bit Bit/Field R/W Reset 7 MPBT R/W X 6 MP R/W 0 5 CTS/PS R/W 0 4 PE0 R/W 0 3 DR R/W 0 2 SS2 R/W 1 1 SS1 R/W 1 0 SS0 R/W 1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W MPBT R/W
Value
Description Multiprocessor Bit Transmit -- When multiprocessor communication format is selected (MP bit is 1), MPBT is used to specify the MPB data bit for transmission. If MPBT is 1, then MPB = 1 is transmitted. If MPBT is 0, then MPBT = 0 is transmitted. MPBT state is undefined during and after RESET. Multiprocessor Mode -- When MP is set to 1, the data format is configured for multiprocessor mode based on the MOD2 (number of data bits) and MOD0 (number of stop bits) bits in CNTLA. The format is as follows. Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits Multiprocessor (MP = 1) format has no provision for parity. If MP is 0, the data format is based on MOD0 MOD1, MOD2, and may include parity. The MP bit is cleared to 0 during RESET.
6
MP
R/W
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Bit Position 5
Bit/Field R/W CTS/PS R/W
Value
Description Clear to Send/Prescale -- When read, CTS/PS reflects the state of the external CTS input. If the CTS input pin is High, CTS/PS is read as 1. When the CTS input pin is High, the TDRE bit is inhibited (that is, held at 0). For channel 1, the CTS1 input is multiplexed with RXS pin (Clocked Serial Receive Data). Thus, CTS/PS is only valid when read if the channel 1 CTS1E bit is 1 and the CST1 input pin function is selected. The read data of CTS/PS is not affected by RESET. When written, CT /PS specifies the baud rate generator prescale factor. If CTS/PS is set to 1, the system clock is prescaled by 30 while if CTS/PS is cleared to 0, the system clock is prescaled by 10.CTS/PS is cleared to 0 during RESET. Parity Even Odd -- PE0 selects even or odd parity. PE0 does not affect the enabling/disabling of parity (MOD1 bit of CNTLA). If PE0 is cleared to 0, even parity is selected. If PE0 is set to 1, odd parity is selected.PE0 is cleared to 0 during RESET. Divide Ratio -- DR specifies the divider used to obtain baud rate from the data sampling clock If DR is reset to 0, divide by 16 is used, while if DR is set to 1, divide by 64 is used. DR is cleared to 0 during RESET. Source/Speed Select -- Specifies the data clock source (internal or external) and baud rate prescale factor. SS2, SS1, and SS0 are all set to 1 during RESET. Table 18 describes the divide ratio corresponding to SS2, SS1 and SS0
4
PEO
R/W
3
DR
R/W
2-0
SS2-0
R/W
The external ASCI channel 0 data clock pins are multiplexed with DMA control lines (CKA0/DREQ and CKA1/TEND0). During RESET, these
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pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are reprogrammed (any other value than SS2, SS1, SS0 = 1) these pins become ASCI data clock inputs. However, if DMAC channel 0 is configured to perform memory to/from I/O (and memory mapped I/O) transfers the CKA0/ DREQ0 pin reverts to DMA control signals regardless of SS2, SS1, SS0 programming. Also, if the CKA1D bit in the CNTLA register is 1, then the CKA1/ TEND0 reverts to the DMA Control output function regardless of SS2, SS1 and SS0 programming. Final data clock rates are based on CTS/PS (prescale), DR, SS2, SS1, SS0 and the Z8X180 system clock frequency (Reference Table 19).
Table 18. SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 Divide Ratio SS0 0 1 0 1 0 1 0 1 Divide Ratio
/1 /2 /4 /8 / 16 / 32 / 64
external clock
Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection.
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ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors Only)
Bit Bit/Field 7 RDRF Int Inhibit R/W 0 6 DCD0 Disable R/W 0 5 CTS0 Disable R/W 0 4 X1 Bit Clk ASCI0 R/W 0 3 BRG0 Mode R/W 0 2 Break Feature Enable R/W 0 1 Break Detect (RO) R/W 0 0 Send Break R/W 0
R/W Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field RDRF Interrupt Inhibit DCD0 Disable CTS0 Disable X1 Bit Clk ASCI0 BRG0 Mode Break Feature Enable Break Detect (RO)
R/W R/W
Value Description 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RDRF Interrupt Inhibit On RDRF Interrupt Inhibit Off DCD0 Auto-enables Rx DCD0 advisory to SW CTS0 Auto-enable Tx CTS0 advisory to SW CKA0 /16 or /64 CKA0 is bit clock As S180 Enable 16-bit BRG counter Break Feature Enable On Break Feature Enable Off Break Detect On Break Detect Off
6 5 4
R/W R/W R/W
3 2
R/W R/W
1
R/W
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Bit Position 0
Bit/Field Send Break
R/W R/W
Value Description 0 1 Normal Xmit Drive TXA Low
Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors Only)
Bit Bit/Field 7 RDRF Int Inhibit R/W 0 6 Reserved 5 4 X1 Bit Clk ASCI1 R/W 0 3 BRG1 Mode R/W 0 2 Break Feature Enable R/W 0 1 Break Detect (RO) R/W 0 0 Send Break R/W 0
R/W Reset
? 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field RDRF Interrupt Inhibit Reserved X1 Bit Clk ASCI1 BRG1 Mode
R/W R/W
Value Description 0 1 0 0 1 0 1 RDRF Interrupt Inhibit On RDRF Interrupt Inhibit Off Reserved. Must be 0 CKA1 /16 or /64 CKA1 is bit clock As S180 Enable 16-bit BRG counter
6-5 4
? R/W
3
R/W
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Bit Position 2
Bit/Field Break Feature Enable Break Detect (RO) Send Break
R/W R/W
Value Description 0 1 0 1 0 1 Break Feature Enable On Break Feature Enable Off Break Detect On Break Detect Off Normal Xmit Drive TXA Low
1
R/W
0
R/W
Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors Only)
Bit R/W Reset 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors Only)
Bit R/W Reset 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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ASCI1 Time Constant Low Register (I/O Address: 1CH) (Z8S180/L180-Class Processors Only)
Bit R/W Reset 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI1 Time Constant High Register (I/O Address: 1DH) (Z8S180/L180-Class Processors Only)
Bit R/W Reset 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Modem Control Signals ASCI channel 0 has CTS0, DCD0 and RTS0 external modem control signals. ASCI channel 1 has a CTS1 modem control signal which is multiplexed with Clocked Serial Receive Data (RXS). CTS0: Clear to Send 0 (Input) The CTS0 input allows external control (start/stop) of ASCI channel 0 transmit operations. When CTS0 is High, the channel 0 TDRE bit is held at 0 whether or not the TDR0 (Transmit Data Register) is full or empty. When CTS0 is Low, TDRE reflects the state of TDR0. The actual transmit operation is not disabled by CT High, only TDRE is inhibited: DCD0: Data Carrier Detect 0 (Input) The DCD0 input allows external control (start/stop) of ASCI channel 0 receive operations. When DCD0 is High, the channel 0 RDRF bit is held at 0 whether or not the RDR0, (Receive Data Register) is full or empty.
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The error flags (PE, FE, and OVRN bits) are also held at 0. Even after the DCD0 input goes Low, these bits do not resume normal operation until the status register (STAT0, is read. This first read of (STAT0, while enabling normal operation, still indicates the DCD0 input is High (DCD0 bit = 1) even though it has gone Low. Thus, the STAT0 register must be read twice to ensure the DCD0 bit is reset to 0: RTS0: Request to Send 0 (Output) RTS0 allows the ASCI to control (start/stop) another communication devices transmission (for example, by connection to that device's CTS input). RTS0 is essentially a 1-bit output port, having no side effects on other ASCI registers or flags. CTS1: Clear to Send 1 (Input) Channel 1 CTS1 input is multiplexed with Clocked Serial Receive Data (RXS). The CTS1 function is selected when the CTS1E bit in STAT1 is set to 1. When enabled, the CTS1 operation is equivalent to CTS0, Modem control signal timing is depicted in Figure 53 and Figure 54.
DCD0 Pin DCD0 Flag Status Register Read
Figure 53.
DCD0 Timing Diagram
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I/O Instruction
I/O write cycle
T1
T2
T3
T1
Phi WR RTS0 Flag
RTS0 Pin
Figure 54.
RTS0 Timing Diagram
Figure 55 illustrates the ASCI interrupt request generation circuit.
IEF1
DCD0 RDRF0 OVRN0 PE0 FE0
RIE0 TDRE0 TIE0
ASCI0 Interrupt Request
RDRF1 OVRN1 PE1 FE1
RIE1 TDRE1 TIE1
ASCI1 Interrupt Request
Figure 55.
ASCI Interrupt Request Circuit Diagram
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ASCI to/from DMAC Operation Operation of the ASCI with the on-chip DMAC channel 0 requires that the DMAC be correctly configured to use the ASCI flags as DMA request signals. ASCI and RESET During RESET, the ASCI status and control registers are initialized as defined in the individual register descriptions. Receive and Transmit operations are stopped during RESET. However, the contents of the transmit and receive data registers (TDR and RDR) are not changed by RESET. ASCI Clock When in external clock input mode, the external clock is directly input to the sampling rate (/ 16// 64) as depicted in Figure 56.
Internal Clock Phi Baud Rate Selection Prescaler / 1 to / 64 / 10 / 30 Sampling Rate / 16 / 64
External Clock fc Phi / 40
Figure 56.
ASCI Clock
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Table 19.
Prescaler Sampling Rate
ASCI Baud Rate Selection
Baud Rate Baud Rate (Example) (BPS) General Divide = 6.144 Ratio MHz / 160 320 640 1280 2560 5120 10240 fc / 16 0/ 640 1280 2560 5120 10240 20480 40960 fc / 64 38400 19200 9600 4800 2400 1200 600 -- 9600 4800 2400 1200 600 300 150 -- -- -- = 4.608 = 3.072 MHz MHz 19200 9600 4800 2400 1200 600 300 -- 4800 2400 1200 600 300 150 75 -- I 0 I 0 CKA Clock Frequency / 10 20 40 80 160 320 640 fc / 10 20 40 80 160 320 640 fc
PS
Divide SS2 SS1 SS0 Divide Ratio DR Rate Ratio 0 0 0 0 16 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 8 16 32 64 -- /1 2 4 8 16 32 64 -- 0 0 1 0 1 0 /1 2 4
I/O
0
/ 10
1 0 0 0 1 64 0 1 1 1 1
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Table 19.
Prescaler Sampling Rate
ASCI Baud Rate Selection (Continued)
Baud Rate Baud Rate (Example) (BPS) General Divide = 6.144 Ratio MHz / 480 960 1920 3840 7680 15360 30720 fc / 16 / 1920 3840 7680 15360 30720 61440 122880 fc / 64 -- -- = 4.608 = 3.072 MHz MHz 9600 4800 2400 1200 600 300 150 -- 2400 1200 600 300 150 75 37.5 -- -- I 0 -- I 0 CKA Clock Frequency / 30 60 120 240 480 960 1920 fc / 30 60 120 240 480 960 1920 fc
PS
Divide SS2 SS1 SS0 Divide Ratio DR Rate Ratio 0 0 0 0 16 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /1 2 4 8 16 32 64 -- /1 2 4 8 16 32 64 --
I/O
1
/ 30
1 1 0 0 0 1 64 0 1 1 1 1
Baud Rate Generator (Z8S180/Z8L180-Class Processors Only)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes. The first is the same as in the Z80180. The second is a 16-bit down counter that divides the processor clock by the value in a 16-bit time constant register, and is identical to the DMSCC BRG. This feature
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allows a common baud rate of up to 512 Kbps to be selected. The BRG can also be disabled in favor of an external clock on the CKA pin. The Receiver and Transmitter subsequently divide the output of the BRG (or the signal from the CKA pin) by 1, 16, or 64, under the control of the DR bit in the CNTLB register, and the X1 bit in the ASCI Extension Control REgister. To compute baud rate, use the following formulas: Where: BRG mode is bit 3 of the ASEXT register PS is bit 5 of the CNTLB register TC is the 16-bit value in the ASCI Time Constant register
If ss2.1.0 = 111, baud rate - f /Clock mode CKA else if BRG mode baud rate = f /(2*(TC+2)*Clock mode) PHI else baud rate -fPHI/((10 + 20*PS) * 2^ss*Clock mode)
The TC value for a given baud rate is:
TC = (fPHI/*2*baud rate*Clock mode)) -2
Clock mode depends on bit 4 in ASEXT and bit 3 in CNTLB, as described in Table 20.
Table 20.Clock Mode Bit Values X1 0 0 1 1 DR 0 1 0 1 Clock Mode 16 64 1 Reserved, do not use
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2^ss depends on the three least significant bits of the CNTLB register, as described in Table 21.
Table 21. 2^ss Values ss2 0 0 0 0 1 1 1 1 ss1 0 0 1 1 0 0 1 1 ss0 0 1 0 1 0 1 0 1 2^ss 1 2 4 8 16 32 64 External Clock from CKA0
The ASCIs require a 50% duty cycle when CKA is used as an input. Minimum High and Low times on CKA0 are typical of most CMOS devices. RDRF is set, and if enabled, an Rx Interrupt or DMA REquest is generated when the receiver transfers a character from the Rx Shift Register to the RX FIFO. The FIFO provides a margin against overruns. When the is more than one character in the FIFO, and software or a DMA channel reads a character, RDRF either remains set or is cleared and then immediately set again. For example, if a receive interrupt service routine does not real all the characters in the RxFIFO, RDRF and the interrupt request remain asserted. The Rx DMA request is disabled when any of the error flags PE or FE or OVRN are set, so that software can identify with which character the problem is associated. If Bit 7, RDRF Interrupt Inhibit, is set to 1, the ASCI does not request a Receive interrupt when its RDRF flag is 1. Set this bit when programming a DMA channel to handle the receive data from an ASCI. The other
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causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0, DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA request is inhibited if PE or FE or OVRN is set, so that software can detect where an error occurred. When the RIE bit is 0, as it is after a Reset, RDRF causes an ASCI interrupt if RIE is 1.
Clocked Serial I/O Port (CSI/O)
The Z8X180 includes a simple, high-speed clock, synchronous serial I/O port. The CSI/O includes transmit/receive (half-duplex), fixed 8-bit data, and internal or external data clock selection. High-speed operation (baud rate 200Kbps at fC = 4 MHz) is provided. The CSI/O is ideal for implementing a multiprocessor communication link between multiple Z8X180s. These secondary devices may typically perform a portion of the system I/O processing, (that is, keyboard scan/decode, LDC interface, for instance).
CSI/O Block Diagram
The CSI/O block diagram is illustrated in Figure 57. The CSI/O consists of two registers-the Transmit/Receive Data Register (TRDR) and Control Register (CNTR).
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Internal Address/Data Bus
Phi
TXS RXS
CSI/O Transmit/Receive Data Register: TRDR (8) CSI/O Control Register: CNTR (8)
Baud Rate Generator
CKS
Interrupt Request
Figure 57.
CSI/O Block Diagram
CSI/O Registers Description CSI/O Control/Status Register (CNTR: I/O Address 0AH)
CNTR is used to monitor CSI/O status, enable and disable the CSI/O, enable and disable interrupt generation, and select the data clock speed and source. CSI/O Control/Status Register (CNTR: 0AH)
Bit Bit/Field R/W Reset 7 EF R 0 6 EIE R/W 0 5 RE R/W 0 4 TE R/W 0 3 -- 2 SS2 R/W 1 1 SS1 R/W 1 0 SS0 R/W 1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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Bit Position 7
Bit/Field R/W EF R
Value
Description End Flag -- EF is set to 1 by the CSI/O to indicate completion of an 8-bit data transmit or receive operation. If EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a CPU interrupt request is generated. Program access of TRDR only occurs if EF is 1. The CSI/O clears EF to 0 when TRDR is read or written. EF is cleared to 0 during RESET and IOSTOP mode. End Interrupt Enable -- EIE is set to 1 to enable EF = 1 to generate a CPU interrupt request. The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET. Receive Enable -- A CSI/O receive operation is started by setting RE to 1. When RE is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the CKS pin. In external dock mode, the dock is input on the CKS pin. In either case, data is shifted in on the RXS pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSI/O automatically clears RE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. RE and TE are never both set to 1 at the same time. RE is cleared to 0 during RESET and ISTOP mode. RXS is multiplexed with CTS1 modem control input of ASCI channel 1. In order to enable the RXS function, the CTS1E bit in CNTA1 must be reset to 0.
6
EIE
R/W
5
RE
R/W
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Bit Position 4
Bit/Field R/W TE R/W
Value
Description Transmit Enable -- A CSI/O transmit operation is started by setting TE to 1. When TE is set to 1, the data clock is enabled. When in internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted out on the TXS pin synchronous with the (internal or external) data clock. After transmitting 8 bits of data, the CSI/O automatically clears TE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. TE and RE are never both set to 1 at the same time. TE is cleared to 0 during RESET and IOSTOP mode. Speed Select -- Selects the CSI/O transmit/receive clock source and speed. SS2, SS I and SS0 are all set to 1 during RESET. Table 22 shows CSI/O Baud Rate Selection.
2-0
SS2-0
R/W
CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and receive operation cannot occur simultaneously). For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, the CSI/O does not work. TRDR is not buffered. Attempting to perform a CSI/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading TRDR during a transmit or receive must be avoided.
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CSI/O Transmit/Receive Register (TRDR: 0BH)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 CSI/O Transmit/Receive Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Table 22. SS2 0 0 0 0 1 1 1 1
CSI/O Baud Rate Selection SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Divide Ratio Baud Rate (200000) (100000) (50000) (25000) (12500) (6250) (3125)
/ 20 / 40 / 80 / 160 / 320 / 640 / 1280
External Clock input (less than / 20)
Note: ( ) indicates the baud rate (BPS) at Phi = 4 MHz.
After RESET, the CKS pin is configured as an external clock input (SS2, SS1, SS0 = 1). Changing these values causes CKS to become an output pin and the selected clock is output when transmit or receive operations are enabled. CSI/O Interrupts The CSI/O interrupt request circuit is shown in Figure 58.
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IEF1
EF EIE
CSI/O Interrupt Request
Figure 58.
CSI/O Interrupt Request Generation
CSI/O Operation The CSI/O is operated using status polling or interrupt driven algorithms.
*
Transmit-Polling a. Poll the TE bit in CNTR until TE = 0. b. Write the transmit data into TRDR. c. Set the TE bit in CNTR to 1. d. Repeat steps 1 to 3 for each transmit data byte.
*
Transmit-Interrupts a. Poll the TE bit in CNTR until TE = 0. b. Write the first transmit data byte into TRDR. c. Set the TE and EIE bits in CNTR to 1. d. When the transmit interrupt occurs, write the next transmit data byte into TRDR. e. Set the TE bit in CNTR to 1. f. Repeat steps 4 and 5 for each transmit data byte.
*
Receive -Polling a. Poll the RE bit in CNTR until RE = 0. b. Set the RE bit in CNTR to 1.
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c. Poll the RE bit in CNTR until RE = 0. d. Read the receive data from TRDR. e. Repeat steps 2 to 4 for each receive data byte.
*
Receive-Interrupts a. Poll the RE bit in CNTR until RE is 0. b. Set the RE and EIE bits in CNTR to 1. c. When the receive interrupt occurs read the receive data from TRDR. d. Set the RE bit in CNTR to 1. e. Repeat steps 3 and 4 for each receive data byte.
CSI/O Operation Timing Notes
* *
Transmitter clocking and receiver sampling timings are different from internal and external clocking modes. Figure 59 to Figure 62 illustrate CSI/O Transmit/Receive Timing. The transmitter and receiver is disabled TE and RE = 0) when initializing or changing the baud rate.
CSI/O Operation Notes
*
Disable the transmitter and receiver (TE and RE = 0) before initializing or changing the baud rate. When changing the baud rate after completion of transmission or reception, a delay of at least one bit time is required before baud rate modification. When RE or TE is cleared to 0 by software, a corresponding receive or transmit operation is immediately terminated. Normally, TE or RE is only cleared to 0 when EF is 1. Simultaneous transmission and reception is not possible. Thus, TE and RE are not both 1 at the same time.
* *
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CSI/O and RESET During RESET each bit in the CNTR is initialized as defined in the CNTR register description. CSI/O transmit and receive operations in progress are aborted during RESET. However, the contents of TRDR are not changed.
CKS
TXS
LSB
MSB
TE EF Read or write of CSI/O Transmit/Receive Data Register
Figure 59.
Transmit Timing Diagram-Internal Clock
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CKS
TXS 2.5 7.5
LSB 2.5 7.5
MSB 2.5 7.5 2.5 7.5
TE EF
Read or write of CSI/O Transmit/Receive Data Register
Figure 60.
Transmit Timing-External Clock
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CKS
RXS
LSB 11 Sampling 11 11 11
MSB
RE EF 17
Read or write of CSI/O Transmit/Receive Data Register
Figure 61.
CSI/O Receive Timing-Internal Clock
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CKS
RXS 11.5
LSB 11.5 16.5 Sampling 16.5 11.5 16.5
MSB
11.5 16.5
RE EF
Read or write of CSI/O Transmit/Receive Data Register
Figure 62.
CSI/O Receive Timing-External Clock
Programmable Reload Timer (PRT)
The Z8X180 contains a two channel 16-bit Programmable Reload Timer. Each PRT channel contains a 16-bit down counter and a 16-bit reload register. The down counter is directly read and written and a down counter overflow interrupt can be programmably enabled or disabled. Also, PRT channel 1 features a TOUT output pin (multiplexed with A18) which can be set High, Low, or toggled. Thus, PRT1 can perform programmable output waveform generation.
PRT Block Diagram
The PRT block diagram is depicted in Figure 63. The two channels feature separate timer data and reload registers and a common status/
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control register. The PRT input clock for both channels is equal to the system clock divided by 20.
Internal Address/Data Bus
Phi / 20
Phi / 20
Timer Data Timer Data Register 0L Register 0H : TMDR0L (8) : TMDR0H (8) Timer Reload Timer Reload Register 0L Register 0H : RLDR0L (8) : RLDR0H (8)
Timer Control Register : TCR (8)
Timer Data Timer Data Register 1L Register 1H : TMDR1L (8) : TMDR1H (8) Timer Reload Timer Reload Register 1L Register 1H : RLDR1L (8) : RLDR1H (8)
TOUT
Interrupt Register
Figure 63.
PRT Block Diagram
PRT Register Description
Timer Data Register (TMDR: I/O Address - CH0: 0CH, 0DH; CH1: 15H, 14H). PRT0 and PRT1 each contain 16-bit timer Data Registers (TMDR). TMDR0 and TMDR1 are each accessed as low and high byte registers (TMDR0H, TMDR0L and TMDR1H, TMDR1L). During RESET, TMDR0 and TMDR1 are set to FFFFH. TMDR is decremented once every twenty clocks. When TMDR counts down to 0, it is automatically reloaded with the value contained in the Reload Register (RLDR). TMDR is read and written by software using the following procedures. The read procedure uses a PRT internal temporary storage register to
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return accurate data without requiring the timer to be stopped. The write procedure requires the PRT to be stopped. For reading (without stopping the timer), TMDR is read in the order of lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read (TMDRnL) stores the higher byte value in an internal register. The following higher byte read (TMDRnH) accesses this internal register. This procedure insures timer data validity by eliminating the problem of potential 16-bit timer updating between each 8-bit read. Specifically, reading TMDR in higher byte-lower byte order may result in invalid data. Note the implications of TMDR higher byte internal storage for applications which may read only the lower and/or higher bytes. In normal operation all TMDR read routines must access both the lower and higher bytes, in that order. For writing, the TMDR down counting must be inhibited using the TDE (Timer Down Count Enable) bits in the TCR (Timer Control Register). Then, any or both higher and lower bytes of TMDR can be freely written (and read) in any order.
CSI/O Transmit/Receive Data Register (TRDR: I/O Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and receive operation cannot occur simultaneously). For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, the CSI/O does not work. TRDR is not buffered. Attempting to perform a CSI/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading TRDR during a transmit or receive must be avoided.
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Timer Data Register 0L (TMDR0L: 0CH)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Data Register 0H (TMDR0H: 0DH)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Reload Register (RLDR: I/O Address = CH0: 0EH, 0FH, CHI, 16H, 17H)
PRT0 and PRT1 each contain 16-bit Timer Reload Registers (RLDR). RLDR0 and RLDR1 are each accessed as low and high byte registers (RLDR0H, RLDR0L and RLDR1H, RLDR1L). During RESET, RLDR0 and RLDR1 are set to FFFFH When the TMDR counts down to 0, it is automatically reloaded with the contents of RLDR.
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Timer Reload Register Channel 0L (RLDR0L: 0EH)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Reload Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Reload Register Channel 0H (RLDR0L: 0FH)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Reload Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Data Register 1L (TMDR1L: 14H)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Data Register 1H (TMDR1H: 15H)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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Timer Reload Register Channel 1L (RLDR1L: 16H)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Reload Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Reload Register Channel 1H (RLDR1H: 17H)
Bit Bit/Field R/W Reset 7 6 5 4 R/W 0 3 2 1 0 Timer Reload Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Timer Control Register (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status. It also controls enabling and disabling of down counting and interrupts along with controlling output pin A18/TOUT for PRT1. Timer Control Register (TCR: 10H)
Bit Bit/Field R/W Reset 7 TIF1 R 0 6 TIF0 R 0 5 TIE1 R/W 0 4 TIE0 R/W 0 3 TOC1 R/W 0 2 TOC0 R/W 0 1 TDE1 R/W 0 0 TDE0 R/W 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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Bit Position 7-6
Bit/Field R/W TIF1-0 R
Value
Description TIF1: Timer Interrupt Flag -- When TMDR1 decrements to 0, TIF1 is set to 1. This generates an interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0 when TCR is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0. When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0. Timer Interrupt Enable -- When TIE1 is set to 1, TIF1 = 1 generates a CPU interrupt request. When TIE1 is reset to 0, the interrupt request is inhibited. During RESET, TIE1 is cleared to 0. When TIE0 is set to 1, TIF0 = 1 generates a CPU interrupt request. When TIE0 is reset to 0, the interrupt request is inhibited. During RESET, TIE0 is cleared to 0. Timer Output Control -- TOC1, and TOC0 control the output of PRT1 using the multiplexed A18/TOUT pin as shown in Table 23. During RESET, TOC1 and TOC0 are cleared to 0. This selects the address function for A18/ TOUT. By programming TOC1 and TOC0 the A18/ TOUT pin can be forced HIGH, LOW, or toggled when TMDR1 decrements to 0. Reference Table 23. Timer Down Count Enable -- TDE1 and TDE0 enable and disable down counting for TMDR1 and TMDR0 respectively. When TDEn (n = 0, 1) is set to 1, down counting is executed for TMDRn. When TDEn is reset to 0, down counting is stopped and TMDRn is freely read or written. TDE1 and TDE0 are cleared to 0 during RESET and TMDRn does not decrement until TDEn is set to 1.
5-4
TIE1-0
R/W
3-2
TOC1-0 R/W
1-0
TDE1-0
R/W
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Table 23. Timer Output Control TOC1 0 0 1 1 TOC0 0 1 0 1 OUTPUT Inhibited Toggled 0 1 A18/TOUT pin is selected as a PRT1 output function! (A18/TOUT pin is selected as an address output function.)
Figure 64 illustrates timer initialization, count down, and reload timing. Figure 65 depicts timer output (A18/TOUT) timing.
Timer Data Register write (0004H) RESET 0 < + < 20 20 20 20 20 20 20 20 20 20
Timer Data Register
FFFFH
0004H
0003H 0002H 0001H 0000H 0003H 0002H 0001H 0000H 0003H
Timer Reload Register Write (0003H)
Reload
Reload
Timer Reload Register TDE Flag TIF Flag
FFFFH 0003H Write 1 to TDE
Timer Data Register Read Timer Control Register Read
Figure 64.
Timer Initialization, Count Down, and Reload Timing Diagram
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Timer Data Reg. = 0001H Phi
Timer Data Reg. = 0000H
TOUT
Figure 65.
Timer Output Timing Diagram
PRT Interrupts
The PRT interrupt request circuit is illustrated in Figure 66.
IEF1
TIF1 TIE1
PRT1 Interrupt Request
TIF0 TIE0
PRT0 Interrupt Request
Figure 66.
PRT Interrupt Request Generation
PRT and RESET
During RESET, the bits in TCR are initialized as defined in the TCR register description. Down counting is stopped and the TMDR and RLDR registers are initialized to FFFFH. The A18/TOUT pin reverts to the address output function.
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PRT Operation Notes
*
TMDR data is accurately read without stopping down counting by reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that order. Also, TMDR is read or written by stopping the down counting. 1 Take care to ensure that a timer reload does not occur during or between lower (RLDRnL*) and higher (RLDRnH*) byte writes. This may be guaranteed by system design/timing or by stopping down counting (with TMDR containing a non-zero value) during the RLDR updating. Similarly, in applications where TMDR is written at each TMDR overflow, the system/software design must guarantee that RLDR can be updated before the next overflow occurs. Otherwise, time base inaccuracy occurs.
*
During RESET, the multiplexed A18/TOUT pin reverts to the address output. By reprogramming the TOC1 and TOC0 bits, the timer output function for PRT channel 1 is selected. The following paragraph describes the initial state of the TOUT pin after TOC1 and TOC0 are programmed to select the PRT channel 1 timer output function. PRT (channel 1) has not counted down to 0. If the PRT has not counted down to 0 (timed out), the initial state of TOUT depends on the programmed value in TOC1 and TOC0.
Secondary Bus Interface
E clock Output Timing The Z8X180 also has a secondary bus interface that allows it to easily interface with other peripheral families.
1. *n = 0, 1
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These devices require connection with the Z8X180 synchronous E clock output. The speed (access time) required for the peripheral devices are determined by the Z8X180 clock rate. Table 24, and Figure 67 through Figure 70 define E clock output timing. Wait States are inserted in Op Code fetch, memory read/write, and I/O read/write cycles which extend the duration of E clock output High. During I/O read/write cycles with no Wait States (only occurs during onchip I/O register accesses), E does not go High.
Table 24. E Clock Timing in Each Condition Condition Op Code Fetch Cycle Memory Read/Write Cycle I/O read Cycle I/O Write Cycle NMI Acknowledge 1st MC INT0 Acknowledge 1st MC BUS RELEASE mode SLEEP mode SYSTEM STOP mode Duration of E Clock Output High T2 rise - T3 fall 1st Tw rise - T3 fall 1st Tw rise - T3 rise T2 rise - T3 fall 1st Tw rise - T3 fall Phi fall - Phi fall (1.5 Phi + nw x Phi) (0.5Phi + nw x Phi) In w x Phi) (1.5 Phi) (0.50 + nw x Phi) (2 Phi or 1 Phi)
Note: nw = the number of Wait States; MC: Machine Cycle
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Op Code Memory Read/ Fetch Cycle Write Cycle I/O Read Cycle
NMI Acknowledge I/O Write Cycle 1st MC
INT0 Acknowledge 1st MC
T1 T2 T3 T1 T2 T3 T1 T2 Tw T3 T1 T2 Phi E M1 MREQ IORQ
T3 T1 T2 T3 T1 T2 Tw*Tw* T3
NOTE : MC = Machine Cycle
* Two wait states are automatically inserted
Figure 67.
E Clock Timing Diagram (During Read/Write Cycle and Interrupt Acknowledge Cycle
Last state Phi BUSREQ BUSACK E
BUS RELEASE mode
TX TX TX TX
E E E
Figure 68.
E Clock Timing in BUS RELEASE Mode
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SLP Instruction 2nd Op Code Fetch Cycle SLEEP mode or SYSTEM STOP mode
T1 T2 T3 T1 T2 Ts Ts Ts Ts
Op Code Fetch Cycle
T1 T2
Phi D0- D7 INT, NMI E E E E
76H
Figure 69.
E Clock Timing in SLEEP Mode and SYSTEM STOP Mode
On-Chip Clock Generator
The Z8X180 contains a crystal oscillator and system clock generator. A crystal can be directly connected or an external clock input can be provided. In either case, the system clock is equal to one-half the input clock. For example, a crystal or external clock input of 8 MHz corresponds with a system clock rate of 4 MHz. Z8S180 and Z8L180-class processors also have the ability to run at X1 and X2 input clock. Table 25 describes the AT cut crystal characteristics (Co, Rs) and the load capacitance (CL1, CL2) required for various frequencies of Z8X180 operation.
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Table 25. Z8X180 Operating Frequencies
Clock Frequency Item Co Rs CL1, CL2 4MHz 4MHz < f 12MHz 12MHz < f 33MHz
< 7 pF <60
10 to 22 pF 10%
< 7 pF <60
10 to 22 pF 10%
< 7 pF <60
10 to 22 pF 10%
If an external clock input is used instead of a crystal, the waveform (twice the clock rate) must exhibit a 50% 10% duty cycle. Note: The minimum clock input High voltage level is VCC -0.6V. The external clock input is connected to the EXTAL pin, while the XTAL pin is left open. Figure 70 depicts the external clock interface.
EXTAL 3 XTAL 2 Open
External Clock Input
Figure 70.
External Clock Interface
Figure 71 illustrates the Z8X180 clock generator circuit while Figures 72 and 72 specify circuit board design rules.
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CL CL
XTAL 2 EXTAL 3 Z8X180 64
Note: Pin numbers are valid only for DIP configuration
Figure 71.
Clock Generator Circuit
Must be avoided
A Signal C CL
B
A, B Signal
2 CL 3 Z8X180
Figure 72.
Circuit Board Design Rules
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20 mm max Crystal CL CL
GND
Signal line layout must avoid shaded areas
1 2 3 Z8X180 Note: Pin mumbers valid only for DIP configuration Top View 64 Phi
Figure 73.
Example of Board Design
Circuit Board design should observe the following parameters.
* * * *
Locate the crystal and load capacitors as close to the IC as physically possible to reduce noise. Signal lines must not run parallel to the clock oscillator inputs. In particular, the clock input circuitry and the system clock output (pin 64) must be separated as much as possible. VCC power lines must be separated from the clock oscillator input circuitry. Resistivity between XTAL or EXTAL and the other pins must be greater than 10M ohms.
Signal line layout must avoid areas marked with the shaded area of Figure 73.
20 mm max
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Miscellaneous
Free Running Counter (I/O Address = 18H) If data is written into the free running counter, the interval of DRAM refresh cycle and baud rates for the ASCI and CSI/O are not guaranteed. In IOSTOP mode, the free running counter continues counting down. It is initialized to FFH during RESET. Free Running counter (FRC: 18H)
Bit Bit/Field R/W Reset 7 6 5 4 R ? 3 2 1 0 Counting Data
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
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Software Architecture
INSTRUCTION SET
The Z80180 is object code-compatible with the Z80 CPU. Refer to the Z80 CPU Technical Manual or the Z80 Assembly Language Programming Manual for further details.
Table 26. Instruction Set Summary
New Instructions Operation SLP MLT INO g, (m) OUT0 (m), g OTIM OTIMR OTDM OTDMR TSTIO m TST g TST m TST (HL) Enter SLEEP mode 8-bit multiply with 16-bit result Input contents of immediate I/O address Output register contents to immediate I/O address Block output - increment Block output - increment and repeat Block output - decrement Block output - decrement and repeat Non-destructive AND, I/O port, and accumulator Non-destructive AND, register, and accumulator Non-destructive AND, immediate data, and accumulator Non-destructive AND, memory data, and accumulator
SLP - Sleep The SLP instruction causes the Z80180 to enter the SLEEP low power consumption mode. See page 32 for a complete description of the SLEEP state.
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MLT- Multiply The MLT performs unsigned multiplication on two 8-bit numbers yielding a 16-bit result. MLT may specify BC, DE, HL, or SP registers. The 8-bit operands are loaded into each half of the 16-bit register and the 16-bit result is returned in that register. OTIM, OTIMR, OTDM, OTDMR - Block I/O The contents of memory pointed to by HL is output to the I/O address in (C). The memory address (HL) and I/O address (C) are incremented in OTIM and OTIMR and decremented in OTDM and OTDMR, respectively. The B register is decremented. The OTIMR and OTDMR variants repeat the above sequence until register B is decremented to 0. Since the I/O address (C) is automatically incremented or decremented, these instructions are useful for block I/O (such as Z80180 on-chip I/O) initialization. When I/O is accessed, 00H is output in high-order bits of address automatically. TSTIO m - Test I/O Port The contents of the I/O port addressed by C are ANDed with immediately specified 8-bit data and the status flags are updated. The I/O port contents are not written (non-destructive AND). When I/O is accessed, 00H is output in higher bits of address automatically. TST g - Test Register Perform an AND instruction on the contents of the specified register with the accumulator (A) and the status flags are updated. The accumulator and specified register are not changed (non-destructive AND). TST m - Test Immediate Perform an AND instruction on the contents of the immediately specified 8-bit data with the accumulator (A) and the status flags are updated. The accumulator is not changed (non-destructive AND).
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TST (HL) - Test Memory The contents of memory pointed to by HL are ANDed with the accumulator (A) and the status flags are updated. The memory contents and accumulator are not changed (non-destructive AND). INO g, (m) - Input, Immediate I/O address The contents of immediately specified 8-bit I/O address are input into the specified register. When I/O is accessed, 00H is output in high-order bits of the address automatically. OUTO (m), g - Output, Immediate I/O address The contents of the specified register are output to the immediately specified 8-bit I/O address. When I/O is accessed, 00H is output in highorder bits of the address automatically.
CPU REGISTERS
The Z80180 CPU registers consist of Register Set GR, Register Set GR' and Special Registers. The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register (F), and three General Purpose Registers (BC, DE, and HL) which may be treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers (B, C, D, E, H, and L) depending on the instruction to be executed. The Register Set GR' is alternate register set of Register Set GR and also contains Accumulator (A'), Flag Register (F') and three General Purpose Registers (BC', DE', and HL'). While the alternate Register Set GR' contents are not directly accessible, the contents can be programmably exchanged at high speed with those of Register Set GR. The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer (SP), and 16-bit Program Counter (PC)
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Figure 74 depicts CPU register configurations.
Register Set GR Accumulator A B Register D Register H Register Flag Register F C Register E Register L Register General Purpose Registers
Register Set GR' Accumulator A' Flag Register F' B' Register D' Register H' Register C' Register E' Register L' Register General Purpose Registers
Special Register Interrupt R Counter Vector Register I R Index Register Index Register Stack Pointer Program Counter IX IY SP PC
Figure 74.
CPU Register Configurations
Accumulator (A, A')
The Accumulator (A) is the primary register used for many arithmetic, logical, and I/O instructions.
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Flag Registers (F, F')
The flag registers store status bits (described in the next section) resulting from executed instructions.
General Purpose Registers (BC, BC', DE, DE', HL, HL')
The General Purpose Registers are used for both address and data operation. Depending on the instruction, each half (8 bits) of these registers (B, C, D, E, H, and I) may also be used.
Interrupt Vector Register (I)
For interrupts that require a vector table address to be calculated (INT0 Mode 2, INT1, INT2, and internal interrupts), the Interrupt Vector Register (I) provides the most significant byte of the vector table address. I is cleared to 00H during reset.
R Counter (R)
The least significant seven bits of the R counter (R) count the number of instructions executed by the Z80180. R increments for each CPU Op Code fetch cycle (each M1 cycle). R is cleared to 00H during reset.
Index Registers (IX, and IY)
The Index Registers are used for both address and data operations. For addressing, the contents of a displacement specified in the instruction are added to or subtracted from the Index Register to determine an effective operand address.
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Stack Pointer (SP)
The Stack Pointer (SP) contains the memory address based LIFO stack. SP is cleared to 0000H during reset.
Program Counter (PC)
The Program Counter (PC) contains the address of the instruction to be executed and is automatically updated after each instruction fetch. PC is cleared to 0000H during reset.
Flag Register (F)
The Flag Register stores the logical state reflecting the results of instruction execution. The contents of the Flag Register are used to control program flow and instruction operation. Flag Register
Bit Bit/Field R/W Reset 7 S R/W 0 6 Z R/W 0 5 Not Used ? ? 4 H R/W 0 3 Not Used ? ? 2 P/V R/W 0 1 N R/W 0 0 C R/W 0
R = Read W = Write X = Indeterminate ? = Not Applicable
Bit Position 7
Bit/Field R/W S R/W
Value 0
Description Sign. S stores the state of the most significant bit
(bit 7) of the result. This is useful for operations with signed numbers in which values with bit 7 = 1 are interpreted as negative.
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Bit Position 6
Bit/Field R/W Z R/W
Value 0
Description Zero. Z is set to 1 when instruction execution produces 0 result. Otherwise, Z is reset to 0. Not used Half Carry. H is used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and thereby adjust the results of BCD addition and subtraction. Not used. P/V: Parity/Overflow. P/V serves a dual purpose. For logical operations P/V is set to 1 if the number of 1 bit in the result is even and P/V is reset to 0 if the number of 1 in the result is odd. For two complement arithmetic, P/V is set to 1 if the operation produces a result which is outside the allowable range (+ 127 to -128 for 8-bit operations, + 32767 to - 32768 for 16-bit operations). Negative. N is set to 1 if the last arithmetic instruction was a subtract operation (SUB, DEC, CP, etc.) and N is reset to 0 if the last arithmetic instruction was an addition operation (ADD, INC, etc.). Carry. C is set to 1 when a carry (addition) or borrow (subtraction) from the most significant bit of the result occurs. C is also affected by Accumulator logic operations such as shifts and rotates.
5 4
Not Used ? H R/W
? 0
3 2
Not Used ? P/V R/W
? 0
1
N
R/W
0
0
C
R/W
0
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Addressing Modes
The Z80180 instruction set includes eight addressing modes.
* * * * * * * *
Implied Register Register Direct Register Indirect Indexed Extended Immediate Relative IO
Implied Register (IMP)
Certain Op Codes automatically imply register usage, such as the arithmetic operations that inherently reference the Accumulator, Index Registers, Stack Pointer, and General Purpose Registers.
Register Direct (REG)
Many Op Codes contain bit fields specifying registers used for operation. The exact bit field definitions vary depending on instruction depicted in Figure 75.
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8-bit Register g or g field ' 0 001 010 011 100 101 110 111
Register B C D E H L -- A
ww 0 0 1 1
field 0 1 0 1
Register BC DE HL SP Register BC DE IX SP Register BC DE IY SP
xx field 00 01 10 11 yy field 00 01 10 11
16-bit Register zz field 00 01 10 11 Register BC DE HL AF
Suffixed H and L ww,xx,yy,zz (ex. wwH,IXL) indicate upper and lower 8-bit of the 16-bit register respectively.
Figure 75.
Register Direct -- Bit Field Definitions
Register Indirect (REG)
The memory operand address is contained in one of the 16-bit General Purpose Registers (BC, DE, and HL) as illustrated in Figure 76.
BC DE HL Operand Memory
Figure 76.
Register Indirect Addressing UM005001-ZMP0400
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Indexed (INDX)
The memory operand address is calculated using the contents of an Index Register (IX or IY) and an 8-bit signed displacement specified in the instruction. Refer to Figure 77
Op Code 1 Op Code 2 displacement (d) Operand IX or IY Memory
Figure 77.
Indexed Addressing
Extended (EXT)
The memory operand address is specified by two bytes contained in the instruction, as depicted in Figure 78.
Op Code n m
m
n
Operand Memory
Figure 78.
Extended Addressing
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Immediate (IMMED)
The memory operands are contained within one or two bytes of the instruction, as depicted in Figure 79.
Op Code m 8-bit operand Op Code n m 16-bit operand
Figure 79.
Immediate Addressing
Relative (REL)
Relative addressing mode is only used by the conditional and unconditional branch instructions (refer to Figure 80). The branch displacement (relative to the contents of the program counter) is contained in the instruction.
Op Code displacement (d)
Program Counter (PC)
Figure 80.
Relative Addressing
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IO (I/O)
IO addressing mode is used only by I/O instructions. This mode specifies I/O address (IORQ is 0) and outputs them as follows. 1. An operand is output to A0-A7. The contents of accumulator is output to A8-A15. 2. The contents of Register B is output to A0 -A7. The contents of Register C is output to A8-A15. 3. An operand is output to A0-A7. 00H is output to A8-A15 (useful for internal I/O register access) 4. The contents of Register C is output to A0 -A7. 00H is output to A8- A15 (useful for internal I/O register access).
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DC Characteristics
This section describes the DC characteristics of the Z8X180 family and absolute maximum rating for these products.
ABSOLUTE MAXIMUM RATING
Table 27. Item Supply Voltage Input Voltage Operating Temperature Extended Temperature Storage Temperature Absolute Maximum Rating Symbol Vcc Vin Topr Text Tstg Value - 0.3 + 7.0 -0.3 Vcc+0.3 0 70 -40 85 - 55 +150 Unit V V C C C
Permanent IC damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of IC.
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Z80180 DC CHARACTERISTICS
VCC = 5V 10%, VSS = OV, Ta = 0to +70 unless otherwise noted.) C,
Table 28. Z80180 DC Characteristics Condition Minimum Typical Maximum Unit VCC -0.6 - 2.0 VCC +0.3 VCC +0.3 V V
Symbol Item VIH1 VIH2 Input High Voltage RESET, EXTAL NMI Input High Voltage except RESET, EXTAL NMI Input Low Voltage RESET, EXTAL NMI Input Low Voltage except RESET, EXTAL NMI Output High Voltage all outputs Output Low Voltage all outputs
VIL1 VIL2
-0.3 -0.3
0.6 0.8 Standard 7 TL VIL - - 0.45 1.0
V V
VOH VOL IIL
IOH = -200 A IOH = -20 A IOL = 2.2 mA
2.4 - VCC -1.2 - - - - -
V V V A
Input Leakage Current VIN = 0.5~ all inputs except XTAL, VCC -0.5 EXTAL Three-State Leakage Current Power Dissipation* (Normal Operation) f = 6 MHz f = 8 MHz f = 33 MHz
ITL ICC
- - - -
- 15 20 25
1.0 40 50 60
A mA mA mA
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Table 28.
Z80180 DC Characteristics (Continued) Condition Minimum Typical Maximum Unit - - - - 3.8 5 6.3 - 12.5 15.0 17.5 12 mA mA mA pF
Symbol Item
Power Dissipation* f = 6 MHz (SYSTEM STOP mode) f = 8 MHz f = 33 MHz CP Pin Capacitance VIN = 0V, f = 1MHz TA = 25C
Notes: * VIN min = VCC -1.0V. VIL max = 0.8V (All output terminals are a no load.) VCC = 5.0V
Z8S180 DC CHARACTERISTICS
VCC = 5V 10%, VSS = OV, Ta = 0to +70 unless otherwise noted. C,
Table 29. Z8S180 DC Characteristics Condition Minimum Typical Maximum Unit VCC -0.6 - 2.0 VCC +0.3 VCC +0.3 V V
Symbol Item VIH1 VIH2 Input High Voltage RESET, EXTAL NMI Input High Voltage except RESET, EXTAL NMI Input High Voltage CKS, CKA0, CKA1 Input Low Voltage RESET, EXTAL NMI Input Low Voltage except RESET, EXTAL NMI
VIH3 VIL1 VIL2
2.4 -0.3 -0.3
VDD + 0.3 V 0.6 0.8 V V
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Table 29.
Z8S180 DC Characteristics (Continued) Condition IOH = -200 A IOH = -20 A IOH = -200 A IOL = 2.2 mA IOL = 2.2 mA Minimum Typical Maximum Unit 2.4 - VCC -1.2 - VCC -0.6 - - - - - 0.45 0.45 1.0 V V A - - V V
Symbol Item VOH1 VOH2 VOL1 VOL2 IIL Output High Voltage All outputs Output High Voltage Output High Phi Output Low Voltage All outputs Output Low Voltage Output Low Phi
Input Leakage Current VIN = 0.5 ~ VCC -0.5 - all inputs except XTAL, ETAL Three-State Leakage Current Power Dissipation* (Normal Operation) Power Dissipation* (SYSTEM STOP Mode) Power Dissipation* (IDLE Mode) Power Dissipation* (STANDBY Mode) VIN = 0.5 ~ VCC -0.5 - f = 10 MHz f = 20 MHz f = 33 MHz f = 10 MHz f = 20 MHz f = 33 MHz f = 20 MHz f = 33 MHz External Oscillator, Internal Clock Stops VIN = 0V, f = 1MHz TA = 25C -
ITL ICC
- 15 30 60 1.5 3 5 4 5 -
1.0 - 50 100 - 6 9 10 10 12
A mA
-
mA
- - -
mA A pF
CP
Pin Capacitance
Notes: * VIN min = VCC -1.0V. VIL max = 0.8V (All output terminals are a no load.) VCC = 5.0V
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Z8L180 DC CHARACTERISTICS
VCC = 3.3V 10%, VSS = OV, Ta = 0to +70 unless otherwise C, noted.)
Table 30. Z8L180 DC Characteristics Condition Minimum Typical Maximum Unit VCC -0.6 2.0 - VCC +0.3 V VCC +0.3 V
Symbol Item VIH1 VIH2 Input High Voltage RESET, EXTAL NMI Input High Voltage except RESET, EXTAL NMI Input Low Voltage RESET, EXTAL NMI Input Low Voltage except RESET, EXTAL NMI Output High Voltage all outputs Output High Voltage Output High Phi Output Low Voltage all outputs Output Low Voltage Output Low Phi
VIL1 VIL2
-0.3 -0.3
0.8 0.8
V V
VOH1 VOH2 VOL VOL2 IIL
IOH = -200 A IOH = -200 A IOL = 4 mA IOL = 4 mA
2.4 VCC -0.6 - - - - - - 0.4 0.4 1.0
V V V V A
Input Leakage Current VIN = 0.5 ~ VCC -0.5 all inputs except XTAL, EXTAL Three-State Leakage Current VIN = 0.5 ~ VCC -0.5
ITL
-
-
1.0
A
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Table 30.
Z8L180 DC Characteristics (Continued) Condition f = 20 MHz f = 20 MHz Minimum Typical Maximum Unit 20 2 100 10 mA mA
Symbol Item ICC Power Dissipation* (Normal Operation) Power Dissipation* (SYSTEM STOP Mode) Power Dissipation* (IDLE Mode) Power Dissipation* (STANDBY Mode) CP Pin Capacitance
f = 20 MHz External Oscillator, Internal Clock Stops VIN = 0V, f = 1MHz TA = 25C -
3 4 -
10 10 12
mA A pF
Notes: * VIN min = VCC -1.0V. VIL max = 0.8V (All output terminals are a no load.) VCC = 3.3V
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Z8L180 Typical ICCA at 4 MHz 5 ICC Active (mA.) 4 3 2 1
2.7
3.0 VDD (Volts)
3.3
Z8S180 Typical ICCA at 20 MHz 50 ICC Active (mA.) 40 30 20 10
2
3
4 VDD (Volts)
5
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AC Characteristics
This section describes the AC characteristics of the Z8X180 family and absolute maximum rating for these products.
AC CHARACTERISTICS-- Z8S180
Table 31. Z8S180 AC Characteristics VDD = 5V 10% or V DD = 3.3V 10%; 33-MHz Characteristics Apply Only to 5V Operation Z8S180-- 20 MHz No. 1 2 3 4 5 6 7 8 9 Symbol Item tCYC tCHW tCLW tCF tCR tAD tAS tMED1 tRDD1 Clock Cycle Time Clock "H" Pulse Width Clock "L" Pulse Width Clock Fall Time Clock Rise Time PHI Rise to Address Valid Delay Address Valid to MREQ Fall or IORQ Fall) PHI Fall to MREQ Fall Delay PHI Fall to RD Fall Delay PHI Rise to RD Rise Delay 0 10 11 12 tM1D1 tAH tMED2 PHI Rise to M1 Fall Delay Address Hold Time from MREQ, IOREQ, RD, WR High PHI Fall to MREQ Rise Delay Min 50 15 15 -- -- -- 5 -- IOC = -- -- 5 -- Max DC -- -- 10 10 30 -- 25 25 25 35 -- 25 Z8S180-- 33 MHz Min 30 10 10 -- -- -- 5 -- -- -- -- 5 -- Max DC -- -- 5 5 15 -- 15 15 15 15 -- 15 ns ns ns Unit ns ns ns ns ns ns ns ns ns
IOC = 1 --
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Table 31.
Z8S180 AC Characteristics (Continued) VDD = 5V 10% or V DD = 3.3V 10%; 33-MHz Characteristics Apply Only to 5V Z8S180-- 20 MHz Z8S180-- 33 MHz Min -- -- 5 0 -- -- 10 5 -- -- -- 10 -- 45 70 5 -- -- -- 80 15 10 Max 15 15 -- -- 15 15 -- -- 20 15 15 -- 15 -- -- -- 15 15 15 -- -- -- ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 26a 27 28
Symbol Item tRDD2 tM1D2 tDRS tDRH tSTD1 tSTD2 tWS tWH tWDZ tWRD1 tWDD tWDS tWRD2 tWRP PHI Fall to RD Rise Delay PHI Rise to M1 Rise Delay Data Read Set-up Time Data Read Hold Time PHI Fall to ST Fall Delay PHI Fall to ST Rise Delay WAIT Set-up Time to PHI Fall WAIT Hold Time from PHI Fall PHI Rise to Data Float Delay PHI Rise to WR Fall Delay PHI Fall to Write Data Delay Time Write Data Set-up Time to WR Fall PHI Fall to WR Rise Delay WR Pulse Width (Memory Write Cycle) WR Pulse Width (I/O Write Cycle) tWDH tIOD1 PHI Fall to IORQ Fall Delay =1 PHI Rise to IORQ Fall Delay =0
Min -- -- 10 0 -- -- 15 10 -- -- -- 10 -- 80 150
Max 25 40 -- -- 30 30 -- -- 35 25 25 -- 25 -- -- -- 25 25 25 -- -- --
Write Data Hold Time from WR Rise 10 IOC -- IOC -- -- 125 20 10
29 30 31 32
tIOD2 tIOD3 tINTS tINTH
PHI Fall to IORQ Rise Delay M1 Fall to IORQ Fall Delay INT Set-up Time to PHI Fall INT Hold Time from PHI Fall
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Table 31.
Z8S180 AC Characteristics (Continued) VDD = 5V 10% or V DD = 3.3V 10%; 33-MHz Characteristics Apply Only to 5V Z8S180-- 20 MHz Z8S180-- 33 MHz Min 25 10 10 -- -- -- 25 25 -- -- -- -- 15 15 -- -- -- -- 20 40 -- -- -- 15 15 30 -- -- 15 15 15 15 -- -- 15 15 15 15 -- -- 10 10 50 Max -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Symbol Item tNMIW tBRS tBRH tBAD1 tBAD2 tBZD NMI Pulse Width BUSREQ Set-up Time to PHI Fall BUSREQ Hold Time from PHI Fall PHI Rise to BUSACK Fall Delay PHI Fall to BUSACK Rise Delay
Min 35 10 10 -- -- 35 35 -- -- -- -- 20 20 -- -- -- -- 25 50 -- -- --
Max -- -- -- 25 25 40 -- -- 20 20 15 15 -- -- 25 25 30 30 -- -- 10 10 75
PHI Rise to Bus Floating Delay Time --
tMEWH MREQ Pulse Width (High) tMEWL MREQ Pulse Width (Low) tRFD1 tRFD2 tHAD1 tHAD2 tDRQS tDRQH tTED1 tTED2 tED1 tED2 PWEH PWEL tEr tEf tTOD PHI Rise to RFSH Fall Delay PHI Rise to RFSH Rise Delay PHI Rise to HALT Fall Delay PHI Rise to HALT Rise Delay DREQ1 Set-up Time to PHI Rise DREQ1 Hold Time from PHI Rise PHI Fall to TENDi Fall Delay PHI Fall to TENDi Rise Delay PHI Rise to E Rise Delay PHI Fall or Rise to E Fall Delay E Pulse Width (High) E Pulse Width (Low) Enable Rise Time Enable Fall Time PHI Fall to Timer Output Delay
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Table 31.
Z8S180 AC Characteristics (Continued) VDD = 5V 10% or V DD = 3.3V 10%; 33-MHz Characteristics Apply Only to 5V Z8S180-- 20 MHz Z8S180-- 33 MHz Min -- Max 2 Unit tcyc
No. 56 57
Symbol Item tSTDI tSTDE CSI/O Transmit Data Delay Time (Internal Clock Operation) CSI/O Transmit Data Delay Time (External Clock Operation) CSI/O Receive Data Set-up Time (Internal Clock Operation) CSI/O Receive Data Hold Time (Internal Clock Operation) CSI/O Receive Data Set-up Time (External Clock Operation) CSI/O Receive Data Hold Time (External Clock Operation) RESET Set-up Time to PHI Fall RESET Hold Time from PHI Fall Oscillator Stabilization Time External Clock Fall Time (EXTAL) RESET Rise Time RESET Fall Time Input Rise Time (except EXTAL, RESET) Input Fall Time (except EXTAL, RESET)
Min -- --
Max 2
7.5 tCY --
C
75 tCYC ns +60 -- -- -- -- -- -- 20 5 5 50 50 50 50 tcyc tcyc tcyc tcyc ns ns ns ns ns ms ms ns ns
+75 58 59 60 61 62 63 64 65 66 67 68 69 70 tSRSI tSRHI tSRSE tSRHE tRES tREH tOSC tEXR tEXF tRR tRF tIR tIF 1 1 1 1 40 25 -- -- -- -- -- -- -- -- -- -- -- -- 20 5 5 50 50 50 50 1 1 1 1 25 15 -- -- -- -- -- -- --
External Clock Rise Time (EXTAL) --
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Timing Diagrams
O pcode F ch Cycl et e T1
2 3
IO W r e Cycl / it e* IO Re ad Cycl* / e T 1 T2 TW T3 T1
T 2
5
TW
T3
PI H ADDRESS W AI T
4 1 6
19
20 19
20
7
12 11
MREQ
8 7 11 13 9 28 13 29 11
I RQ O
RD
9 22 26 14
11 25
WR
M1
10 17 15 16 18 15 16 21
ST
Dat I aN
23 24 27
Dat OUT a
62
RESET
68
63
62
63
67
67
68
Figure 81.
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Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle except there are no automatica Wait States (TW), and MREQ is active instead of IORQ.
PI H
31 32
I NT0,1,2
33
NMI
M1
10 30 28 14
I ORQ
15 16 29
Data I N
39
MREQ
41
40 42
RF SH
34 35
34
35
BUSREQ
36 37
BUSACK
38 38
A19 - D7- 0, 0
MREQ, RD W R, I ORQ
43
Out put B f r Of uf e f
44
H AL T
Figure 82.
AC Timing Diagram 2
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IO Re ad Cycl / e T1 PI H ADDRESS 28 I RQ O 9 RD 13 29 T2 Tw T3 T1
IO W rit Cycl / e e T2 Tw T3
28
29
22 WR IO Re ad Cycl / e CPU Tim ing (I C = 0) O IO W rit Cycl / e e
25
Figure 83.
CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle)
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T1 PI H
CPU or DMA Re ad/ r e Cycl (O nl DMA W r e Cycl f TENDi) W it e y it e or T2 TW T3 T1
45 DREQ1 (lv l e e sens e ) DREQ1 (e dge s e ns e ) 47
* 46
* 45 46*
CPU Cycl e St r s at
18
48 TENDi ST
Not s : e * D RQS and TD RQH are spe cif f t e rising e dge of t e cl f l e d by T3. T ied or h h ock ol ow * TD RQS and TDRQH are s pe cif f t e rising edge of t e cl . * ied or h h ock
DMA Cycl e St r s at
17
Figure 84.
DMA Control Signals
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T1 PI H
T2
TW ~ ~
TW
T3
E (Mem ory Re ad/ rit ) We E (IO Re ad) /
49 49
50 50
~ ~ ~ ~ 49 50 ~ ~ 15 ~ ~
E (IO W rit ) / e D 0- 7 D Figure 85.
16
E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle)
~ ~
PI H E BUS REL EASE m ode SL EEP m ode SYSTEM STO P m ode
49
50
Figure 86.
E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and SYSTEM STOP Mode
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T2 PI H E Exam pl e IO Re ad / O pcode F t e ch E (IO W rit ) / e
TW
T3 50
T1
T2 49 53
52
49
50 51 54
54
53
Figure 87.
E Clock Timing (Minimum Timing Example of PWEL and PWEH)
PI H Tim e r D at a Re g. = 0000H A 18/ O UT T 55
Figure 88.
Timer Output Timing
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SL I r ion F t P nst uct e ch T3 PI H T1 T2 TS TS ~ ~ 31 I NTi 32 ~ ~
Ne xt O pcode F t e ch T1 T2
NM I
~ ~
33
~ ~
A A 19 - 0
~ ~ ~ ~
M REQ, M 1 RD H AL T
43
44
~ ~
Figure 89.
SLP Execution Cycle Timing Diagram
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CSIO Cl / ock 56 Transm it Dat a (I e rnal ock ) nt Cl 57 Transm it D at a (Ext rnal ock ) e Cl 11t cyc 58 Re ce iv D at e a (I e rnal ock ) nt Cl 11.5t cyc cyc 16.5t Re ce iv D at e a (Ext rnal ock ) e Cl 60 61 11.5t 16.5t cyc cyc 59 11t cyc 58 59 57 56
60
61
Figure 90.
CSI/O Receive/Transmit Timing Diagram
65 EXTAL VIL1 VIH1 VIH1
66 VIL1
Figure 91.
External Clock Rise Time and Fall Time
70
69
Figure 92.
Input Rise Time and Fall Time (Except EXTAL,RESET)
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STANDARD TEST CONDITIONS
The previous DC Characteristics and Capacitance sections apply to the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows in to the referenced pin. All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK, which is referenced to the 10% and 90% points). The Ordering Information section lists temperature ranges and product numbers. Package drawings are in the Package Information section. Refer to the Literature List for additional documentation.
+5V 2.1K From Output Under Test 100 pf v 200 A
Figure 93.
Test Setup
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Instruction Set
This section explains the symbols in the instruction set.
REGISTER
g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a pair of 8-bit registers. Table 32 describes the correspondence between symbols and registers.
Table 32. Register Values g,g' Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A Note: Suffixed H and L to ww, xx, yy, zz (ex. wwH, IXL) indicate upper and lower 8-bit of the 16-bit register respectively. ww 00 01 10 11 Reg. BC DE HL SP xx 00 01 10 11 Reg. BC DE IX SP yy 00 01 10 11 Reg. BC DE IY SP zz 00 01 10 11 Reg. BC DE HL AF
BIT
b specifies a bit to be manipulated in the bit manipulation instruction. Table 33 indicates the correspondence between b and bits.
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Table 33.
Bit Values b 000 001 010 011 100 101 110 111 Bit 0 1 2 3 4 5 6 7
CONDITION
f specifies the condition in program control instructions. Table 34 describes the correspondence between f and conditions.
Table 34. Instruction Values f 000 001 010 011 100 101 110 111 NZ Z NC C PO PE P M Condition Nonzero Zero Non Carry Carry Parity Odd Parity Even Sign Plus Sign Minus
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RESTART ADDRESS
v specifies a restart address. Table 35 describes the correspondence between v and restart addresses.
Table 35. Address Values v 000 001 010 011 100 101 110 111 Address 00H 08H l0H 18H 20H 28H 30H 38H
FLAG
The symbols listed in Table 36 indicate the flag conditions.
Table 36. Flag Conditions
*
Not Affected
Affected x Undefined S Set to 1 R Reset to 0 P Parity V Overflow
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MISCELLANEOUS
Table 37 lists the operations mnemonics.
Table 37. Operations Mnemonics ( )M ( )I mn r R b.gr S D
*
Data in the memory address Data in the I/O address 16-bit data 8-bit register 16-bit register A content of bit b in the register gr Source Destination AND operation OR operation EXCLUSIVE OR operation Added new instructions to Z80
m or n 8-bit data
b.( )M A content of bit b in the memory address d or j 8-bit signed displacement
+ **
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DATA MANIPULATION INSTRUCTIONS
Table 38. Arithmetic and Logical Instructions (8-bit)
Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation 7 6 4 2 1 0
SZ
H P/V N C
ADD
ADD A,g ADD A, (HL) ADD A, m
10 000 g 10 000 110 11 000 110 S
S S
D D D
1 1 2
4 6 6
Ar + gr Ar Ar + (HL)M Ar Ar + m Ar
V V V
R R R
ADD A,(IX + d) 11 011 101 10 000 110 ADD A,(IY + d) 11 111 101 10 000 I10 ADC ADC A,g ADC A,(HL) ADC A,m 10 001 g 10 001 110 11 001 110 S ADC A,(IX + d) 11 011 101
S
D
3
14
Ar + (IX + d)M Ar
V
R
S
D
3
14
Ar + (IY + d))M Ar
V
R
S S
D D D
1 1 2
4 6 6
Ar + gr + c Ar Ar + (HL)M + c Ar Ar + m + c Ar
V V V
R R R
S
D
3
14
Ar + (lX + d))M + c Ar
V
R
10 001 110 ADC A,(IY + d) 11 111 101 10 001 110 S D 3 14 Ar + (IY + d))M + c Ar V R
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Flags Addressing 7 6 4 2 1 0
Operation Name
Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States Operation
SZ
H P/V N C
AND
AND g AND (HL) AND m
10 100 g 10 100 110 11 100 110 S
S S
D D D
1 1 2
4 6 6
Ar*gr Ar Ar*(HL)M Ar Ar*m Ar
SP SP SP
RR RR RR
AND (IX + d)
11 011 101 10 100 110
S
D
3
14
Ar*(1X + d))M Ar
SP
RR
AND (IY + d)
11 111 101 10 100 110
S
D
3
14
Ar*(1Y + d)v Ar
SP
RR
Compare
CP g CP (HL) CP m
10 111 g 10 111 110 11 111 110 S
S S
D D D
1 1 2
4 6 6
Ar-gr Ar-(HL)M Ar-m
V V V
S S S
CP (IX + d)
11 011 101 10 111 110
S
D
3
14
Ar-(IX + d))M
V
S
CP (IY + d)
11 111 101 10 111 110
S
D
3
14
Ar-(IY + d))M
V
S
Compleme nt
CPL
00 101 111
S/D
1
3
Ar Ar
**S *
S*
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Flags Addressing 7 6 4 2 1 0
Operation Name
Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States Operation
SZ
H P/V N C
DEC
DEC g DEC (HL) DEC (IX + d)
00 g 101 00 110 101 11 011 101 00 110 101 S/D
S/D S/D
1 1 3
4 10 18
gr-1 gr (HL)M-1 (HL)M (IX + d))M-I (IX + d))M
V V V
S* S* S*
DEC (IY + d)
11 111 101 00 1101 01
S/D
3
18
(IY + d)M-1 (IY + d)M
V
S*
INC
INC g INC (HL) INC (IX + d)
00 g 100 00 110 100 11 011 101 00 110 100 S/D
S/D S/D
1 1 3
4 10 18
gr + I gr (HL)M + I (HL)M (IX + d))M + 1 (1X + d))M
V V V
R* R* R*
INC (IY + d)
11 111 101 00 110 100
S/D
3
18
(IY + d)v + 1 (IY + d)v
V
R*
MULT
MLT ww**
11 101 101 01 WWI 100
S/D
2
17
wwHr wwLr wwI
****
**
NEGATE
NEG
11 101 101 01 000 100
S/D
2
6
0-Ar Ar
Y
S
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Flags Addressing 7 6 4 2 1 0
Operation Name
Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States Operation
SZ
H P/V N C
OR
OR g OR (HL) OR m
10 110 g 10 110 110 11 110 110 S
S S
D D D
1 1 2
4 6 6
Ar + gr Ar Ar + (HL)M Ar Ar + m Ar
RP RP RP
RR RR RR
OR (IX + d)
11 011 101 10 110 110
S
D
3
14
Ar + (IX + d)M Ar
RP
RR
OR (IY + d)
11 111 101 10 110 110
S
D
3
14
Ar + (IY + d)M Ar
RP
RR
SUB
SUB g SUB (HL) SUB m
10 010 g 10 010 110 11 010 110 S
S S
D D D
1 1 2
4 6 6
Ar-gr Ar Ar-(HL)M Ar Ar-m Ar
V V V
S S S
SUB (IX + d)
11 011 101 10 011 110
S
D
3
14
Ar-(IX + d)M-c Ar
V
S
SUB (IY + d)
11 111 101 10 010 110
S
D
3
14
Ar-(IY + d)M-c Ar
V
S
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Flags Addressing 7 6 4 2 1 0
Operation Name
Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States Operation
SZ
H P/V N C
SUBC
SBC A,g SBC A,(HL) SBC A,m
10 011 g 10 011 110 11 011 110 S
S S
D D D
1 1 2
4 6 6
Ar-gr-c Ar Ar-(HL)M-c Ar Ar-m-c Ar
V V V
S S S
SBC A,(IX + d) 11 011 101 10 011 110 SBC A,(IY + d) 11 111 101 10 011 110 TEST TST g** 11 101 101 00 g 100 TST {HL)** 00 110 100 TST m** 11 101 101 S 01 100 100 XOR XOR g XOR (HL) XOR m 10 101 g 10 101 110 11 101 110 S XOR (IX + d) 11 011 101 10 101 110 11101101
S
D
3
14
Ar-(IX + d)M-c Ar
V
S
S
D
3
14
Ar-(IY + d)M-c Ar
V
S
S
2
7
Ar* gr
SP
RR
S
2
10
Ar* M (HL)
SP
RR
3
9
Ar* m
SP
RR
S S
D D D
1 1 2
4 6 6
Ar + gr Ar Ar + (HL)M Ar Ar + m Ar
RP RP RP
RR RR RR
S
D
3
14
Ar + (IX + d))M Ar
RP
RR
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Table 38.
Arithmetic and Logical Instructions (8-bit) (Continued)
Flags Addressing 7 6 4 2 1 0
Operation Name
Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States Operation
SZ
H P/V N C
XOR (IY + d)
11 111 101 10 101 110
S
D
3
14
Ar + (IY + d))M Ar
RP
RR
Table 39.
Rotate and Shift Instructions
Flags Addressing State Immed Ext Ind Reg Regi Imp Rel Bytes s 7642 Operation 10
Operation Name Mnemonics
Op Code
S Z H P/V N C
Rotate and Shift Data
RL A RL g
00 010 1111 11 001 011 00 010 g S/D
S/D
1 2
3 7 C b7 b0
**R * RP RP RP
R R R R
RL (HL)
11 001 011 00 010 110
S/D
2
13
RL (IX + d)
11 011 101 11 001 011 00 010 110
S/D
4
19
RL (IY + d)
11 111 101 11 001 011 00 010 110
S/D
4
19 b7 b0
Ar
RP
R
(HL)M S/D S/D 1 2 3 7 b7 b0 **R * RP RP R R R
RLC A RLC g
00 000 111 11 001 011 00 000 g
RLC (HL)
11 001 011 00 000 110
S/D
2
13
b7
b0
C
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Table 39.
Rotate and Shift Instructions (Continued)
Flags Addressing 7642 Operation 10
Operation Name Mnemonics
Op Code
State Immed Ext Ind Reg Regi Imp Rel Bytes s
S Z H P/V N C
RLC (IX + d)
11 011 101 11 001 011 00 000 110
S/D
4
19
RP
R
RLC (IY + d)
11 111 101 11 001 011 00 000 110
S/D
4
19
RP
R
RLD
11 101 101 01 101 111
S/D
2
16 C b7 b0
RP **R * RP RP RP
R* R R R R
RRA RRg
00 011 111 11 001 011 00 011 g S/D
S/D
1 2
3 7
RR (HL)
11 001 011 00 011 110
S/D
2
13
RR (IX + d)
11 011 101 11 001 011 00 011 110
S/D
4
19
RR (IY + d)
11 111 101 11 001 011 00 011 110
S/D
4
19
b0
b7
C
RP
R
RRCA RRC g
00 001 111 11 001 011 00 001 g S/D
S/D
1 2
3 7
**R * RP RP RP
R R R R
RRC (HL)
11 001 011 00 001 110
S/D
2
13
RRC (IX + d)
11 011 101 11 001 011 00 001 110
S/D
4
19
RRC (IY + d)
11 111 101
S/D
4
19
RP
R
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Table 39.
Rotate and Shift Instructions (Continued)
Flags Addressing 7642 Operation 10
Operation Name Mnemonics
Op Code
State Immed Ext Ind Reg Regi Imp Rel Bytes s
S Z H P/V N C
11 001 011 00 001 110 RRD 11 101 101 01 100 111 SLA g 11 001 011 00 100 g SLA (HL) 11 001 011 00 100 110 SLA (IX + d) 11 011 101 11 001 011 00 100 110 SLA (IY + d) 11 111 101 11 001 011 00 100 110 SRA g 11 001 011 00 101 g SRA (HL) 11 001 011 00 101 110 SRA (IX + d) 11 011 101 11 001 011 00 101 110 SRA (IY + d) 11 111 101 11 001 011 00 101 110 SRL g 11 001 011 00 111 g S/D 2 7 0 b7 b0 C RP R S/D 4 19 RP R S/D 4 19 RP R S/D 2 13 b7 b0 C RP R S/D 2 7 RP R S/D 4 19 RP R S/D 4 19 C b7 b0 0 RP R S/D 2 13 b7 b0 S/D 2 7 b7 b0 (HL)M S/D 2 16 Ar RP RP R R RP R*
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Table 39.
Rotate and Shift Instructions (Continued)
Flags Addressing 7642 Operation 10
Operation Name Mnemonics
Op Code
State Immed Ext Ind Reg Regi Imp Rel Bytes s
S Z H P/V N C
SRL (HL)
11 001 011 00 111 110
S/D
2
3
RP RP
R R
SRL (IX + d)
11 011 101 11 001 011 00 111 110
S/D
4
19
SRL (IY + d)
11 111 101 11 001 011 00 111 110
S/D
4
19
RP
R
Bit Set
SET b,g
11 001 011 11 b g
S/D
2
7
1 b* gr
**** **** ****
** ** **
SET b,(HL)
11 001 011 11 b 110
S/D
2
13
1 b* M (HL)
SET b,(IX + d) 11 011 101 11 001 011 11 b 110 SET b,(IY + d) 11 111 101 11 001 011 11 b 110 Bit Reset RES b,g 11 001 011 10 b g RES b,(HL) 11 001 011 10 b 110 RES b,(IX + d) 11 011 101 11 001 011 10 b 110
S/D
4
19
1 b* + d)M (IX
S/D
4
19
l b* + d)M (IY
****
**
S/D
2
7
0 b* gr 0 6*b* M (HL) 0 * (IX + d)M b*
**** **** ****
** ** **
S/D
2
13
S/D
4
19
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Table 39.
Rotate and Shift Instructions (Continued)
Flags Addressing 7642 Operation 10
Operation Name Mnemonics
Op Code
State Immed Ext Ind Reg Regi Imp Rel Bytes s
S Z H P/V N C
Bit Reset RES b,(IY + d) 11 011 101 11 001 01l 10 b 110 Bit Test BIT b, g 11 001 011 01bg BIT b,(HL) 11 001 011 01 b 110 BIT b,(IX + d) 11 011 101 11 001 011 01 b 110 BIT b,(IY + d) 11 111 101 11 001 011 01 b 110
S/D
4
19
0 b* + d)M (IY
****
**
S
2
6
b* z gr b* M z (HL) b* + d)M z (IX
XSX XSX XSX
R* R* R*
S
2
9
S
4
15
S
4
15
b* + d)M z (IY
XSX
R*
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Table 40.
Arithmetic Instructions (16-bit)
Flags Addressing 7 Operation S 6 Z 4 H 2 1 0
Operation Name Mnemonics
Op Code
Immed
Ext
Ind
Reg RegI Imp Rel Bytes States
P/V N C
ADD
ADD HL,ww ADD IX,xx
00 ww1 001 11 011 101 00 xx1 001
S S
D D
1 2
7 10
HLR + wwR HLR IX R + xx R *IXR IYR + yyR IYR HLR + wwR + c HLR ww R -1 * R ww 1XR -1 IX R 1YR -1 IYR ww R + 1 ww R 1XR + 1 IX R 1YR + 1 IYR HLR-wwR-c HLR
**X **X **X
* * *
R R R R
ADD IY,yy
11 111 101 00 yy1 001
S
D
2
10
ADC
ADC HL,ww
11 101 101 01 ww1 010
S
D
2
10
X
V
DEC
DEC ww DEC IX
00 ww1 011 11 011 101 00 101 011
S/D S/D
1 2
4 7
**** **** **** **** **** ****
** ** ** ** ** ** S
DEC IY
11 111 101 00 101 011
S/D
2
7
INC
INC ww INC IX
00 ww 0011 11 011 101 00 100 011
S/D S/D
1 2
4 7
INC IY
11 111 101 00 100 011
S/D
2
7
SBC
SBC HL ww
11 101 101 01 ww0 010
S
D
2
10
X
V
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DATA TRANSFER INSTRUCTIONS
Table 41. 8-Bit Load
Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation 7642 S Z H P/V 10 NC
Load 8-Bit Data
LD A,I
11 101 101 01 010 111
S/D
2
6
1r Ar
R IEF2 R * R IEF2 R * **** **** **** ** ** **
LD A,R
11 101 101 01 011 111
S/D
2
6
Rr Ar (BC)M Ar (DE)M Ar (mn)M Ar
LD A,(BC) LD A,(DE) LD A,(mn)
00 001 010 00 011 010 00 111 010 S
S S
D D D
1 1 3
6 6 12
LD L,A
11 101 101 01 000 111
S/D
2
6
Ar Ir
**** **** **** **** ****
** ** ** ** **
LD R,A
11 101 101 01 001 111
S/D
2
6
Ar Rr
LD (BC),A LD(DE),A LD (mn),A
00 000 010 00 010 010 00 110 010 D
D D
S S S
1 1 3
7 7 13
Ar (BC)M Ar (DE)M Ar (mn)M
LD gg' LD g,(HL) LD g,m
01 g g' 01 g 110 00 g 110 S
S/D D D S
1 1 2
4 6 6
gr' gr (HL)M gr m gr
**** **** **** ****
** ** ** **
LD g,(IX + d)
11 011 101 01 g 110
S
D
3
14
(IX + d)Mgr
LD g,(IY + d)
11 111 101 01 g 110
S
D
3
14
(IY + d)M gr
****
**
LD (HL),m
00 110 110 S
D
2
9
m (HL)M
****
**
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Table 41.
8-Bit Load (Continued)
Flags Addressing 7642 Rel Bytes States Operation S Z H P/V 10 NC
Operation Name
Mnemonics
Op Code
Immed Ext
Ind
Reg
RegI Imp
Load 8-Bit Data
LD (IX + d),m
11 011 101 S 00 110 110
D
4
15
m (IX + d)M
****
**
LD (IY + d),m
11 111 101 S 01 110 g
D
4
15
m (IY + d)M
****
**
LD (HL),g LD (IX + d),g
01 110 g 11 011 101 01 110 g D
S S
D
1 3
7 15
gr (HL)M gr (IX+d)M
**** ****
** **
LD (IY + d),g
11 111 101 01 110 g
D
S
3
15
gr (IY + d)M
****
**
(1) In the case of R1 and Z Mask, interrupts are not sampled at the end of LD A, I or LD A,R.
Table 42.
16-Bit Load
Flags Addressing 7642 Rel Bytes States Operation 10
Operation Name Mnemonics
Op Code
Immed
Ext
Ind
Reg RegI Imp
S Z H P/V N C
Load 16-Bit Data
LD ww,mn
00 ww0 001
S
D
3
9
mn wwR
**** **
LD IX,mn
11 011 101 00 100 001
S
D
4
12
mn IXR
**** **
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Table 42.
16-Bit Load (Continued)
Flags Addressing 7642 Rel Bytes States Operation 10
Operation Name Mnemonics
Op Code
Immed
Ext
Ind
Reg RegI Imp
S Z H P/V N C
Load 16-Bit Data
LD IY,mn
11 111 101 00 100 001
S
D
4
12
mn IYR
**** **
LD SP,HL LD SP,IX
11 111 001 11 011 101 11 111 001
S/D S/D
1 2
4 7
HIR SPR IX R-SPR IYR SPR (mn + 1)M wwHr (mn)M wwLr
**** ** **** ** **** ** **** **
LD SP,IY
11 111 101 11 111 001
S/D
2
7
LD ww,(mn)
11 101 101 01 ww1 011
S
D
4
18
LD HL,(mn)
00 101 010
S
D
3
15
(mn + 1)M Hr (mn)M Lr
**** **
LD IX,(mn)
11 011 101 00 101 010
S
D
4
18
(mn + 1)M IXHr (mn)M IXLr
**** **
LD IY,(mn)
11 111 101 00 101 010
S
D
4
18
(mn + 1)M IYHr (mn)M IYLr
**** **
LD (mn),ww
11 101 101 01 ww0 011
D
S
4
19
wwHr (mn + 1)M wwLr (mn)M
**** **
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Table 42.
16-Bit Load (Continued)
Flags Addressing 7642 Rel Bytes States Operation 10
Operation Name Mnemonics
Op Code
Immed
Ext
Ind
Reg RegI Imp
S Z H P/V N C
Load 16-bit Data
LD (mn),HL
00 100 010
D
S
3
16
Hr (mn + 1)M Lr (mn)M
**** **
LD (mn),IX
11 011 101 00 100 010
D
S
4
19
IXHr-(mn + 1)M IXLr (mn)M
**** **
LD (mn),IY
11 111 101 00 100 010
D
S
4
19
IYHr (mn + 1)M IYLr (mn)M
**** **
Table 43.
Block Transfer
Flags Addressing 7 Operation 6 4 2 10
Operation Name Mnemonics Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
SZ
H P/V N C
Block Transfer Search Data
(3) CPD 11 101 101 10 101 001 S S 2 12 Ar = (HL)M BCR-1 BCR HLR-1 HLR CPDR 11 101 101 10 111 001 S S 2 14 12 BCR 0 Ar (HL)M BCR = 0 or Ar = (HL)M Q Ar-(HL)R BCR-1-BCR HLR-1 HLR (3)
(2) S*
(2) S*
Repeat Q until Ar = (HL)M or BCR = 0 (3) (2)
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Table 43.
Block Transfer (Continued)
Flags Addressing 7 Operation 6 42 10
Operation Name Mnemonics Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
SZ
H P/V N C
CPI
11101101 10100001
S
S
2
12
Ar-(HL)M BCR-1 BCR HLR + 1 HLR
S*
(3)
(2) S*
CPIR
11101101 10110001
S
S
2
14 12
BCR 0 Ar*(HL)M BCR = 0 or Ar = (HL)M Q Ar-(HL)M BCR-1 BCR HLR + 1 HLR
Repeat Q until Ar = (HL)M or BCR = 0 LDD 11 101 101 10 101 000 S/D 2 12 (HL)M (DE)M BCR -1 BCR DER-1 DER HLR-1 HLR LDDR 11 101 101 10 111 000 S/D 2 14(BCR 0) 12(BCR = 0) Q (HL)M (DE)M BCR -1 BCR DER -1 DER HLR -1 HLR ** R R R* (2) ** R R*
Repeat Q until BCR = 0 LDI 11 101 101 10 100 000 S/D 2 12 (HL)M DE)R BCR-1 BCR DER + 1 DER HLR + 1 HLR LDIR 11 101 101 10 110 000 S/D 2 14(BCR0) 12(BCR = 0) Q (HL)M (DE)M BCR-1 BCR DER + 1 DER HLR + 1 HLR ** R R R* (2) ** R R*
Repeat Q until BCR = 0 (2) P/V = 0: BCR-1 = 0 P/V = 1: BCR-1 0 (3) Z = 1: Ar = (HL)M Z = 0 :Ar (HL)M
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Table 44.
Stock and Exchange
Flags Addressing 7 Operation 6 4 2 10
Operation Name Mnemonics
Op Code
Immed Ext
Ind
Reg
RegI Imp Rel Bytes States
S Z H P/V N C
PUSH
PUSH zz
11zz 0101
S
D
1
11
zzLr (SP-2)M zzHr (SP-1)M SPR-2 SPR
****
**
PUSH IX
11 011 101 11 100 101
S/D
2
14
IXLr (SP-2)M IXHr (SP-1)M SPR-2 SPR
****
**
PUSH
PUSH IY
11 111 101 11 100 101
S/D
2
14
IYLr (SP-2)M IYHr (SP-1)M SPR-2 SPR
****
**
POP
POP zz
11 zz0 001
D
S
1
9
(SP + 1)M xxHr(4) (SP)M zzLx SPR + 2 SPR (SP + 1)M IXHr (SP)M IXLr SPR + 2 SPR
****
**
POP IX
11 011 101 11 100 001
S/D
2
12
****
**
POP IY
11 111 101 11 100 001
S/D
2
12
(SP + 1)M IYHr (SP)M-IYLr SPR + 2 SPR
****
**
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Table 44.
Stock and Exchange (Continued)
Flags Addressing 7 Operation 6 4 2 10
Operation Name Mnemonics
Op Code
Immed Ext
Ind
Reg
RegI Imp Rel Bytes States
S Z H P/V N C
Exchange EX AFAF' EX DE, HL EX X
00 001 000 11 101 011 11 011 001
S/D S/D S/D
1 1 1
4 3 3
AFR-AFR' DER-HLR BCR-BCR' DER DER' HLR HLR'
**** **** ****
** ** **
EX (SP),HL
11 100 011
S/D
1
16
Hr (SP + 1)M Lr (SP)M IXHr (SP + 1)M IXLr-(SP)M IYHr-(SP + 1)M IYLr (SP)M
**** **** ****
** ** **
EX (SP),IX
11 011 101
S/D
2
19
EX (SP),IY
11 111 101 11 100 011
S/D
2
19
(4) In the case of POP AF, Flag is written as current contents of the stack
.
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PROGRAM AND CONTROL INSTRUCTIONS
Table 45. Program Control Instructions
Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg RegI Imp Rel Bytes States Operation 7 64 2 1 0
S Z H P/V N C
Call
CALL mn
11 001 101
D
3
16
PCHr (SP-1)M PCLr (SP-2)M mn PCR SPR-2 SPR
****
**
CALL f,mn
11 f 100
D
3
6 (f : false) 16 (f: true) 9 (Br 0) 7 (Br = 0)
continue : f is false CALL mn: f is true
****
**
Jump
DJNZj
00 010 000
D
2 2
Br-1 Br continue: Br = 0 PCR + j PCR: Br 0
****
**
JP f,mn
11 f 010
D
3 3
6 (f: false) 9 (f: true)
mn PCR: f is true continue: f is false
****
**
JP mn
11 000 011
D
3
9
mn PCR
****
**
JP (HL) JP (IX)
11 101 001 11 011 101 11 101 001
D D
1 2
3 6
HLR PCR IX R PCR IYR PCR PCR + j PCR continue: C = 0 PCR + j PCR: C = 1 continue : C = 1 PCR + j PCR : C = 0
**** **** **** **** **** ****
** ** ** ** ** **
JP (IY)
11 111 101 11 101 001
D
2
6
JR j
00 011 000
D
2
8
JR Cj
00 111 000
D
2 2
6 8 6 8
JR NCj
00 110 000
D
2 2
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Table 45.
Program Control Instructions (Continued)
Flags Addressing 7 Operation 64 2 1 0
Operation Name Mnemonics
Op Code
Immed Ext Ind
Reg RegI Imp Rel Bytes States
S Z H P/V N C
Jump
JR Zj
00 101 000
D
2 2
6 8 6 8 9
continue : Z = 0 PCR, + j PCR : Z = 1 continue : Z = 1 PCR + j PCR : Z = 0 (SP)M PCLr (SP + 1)M PCHr SPR + 2 SPR
****
**
JR NZj
00 100 000
D
2 2
Return
RET
11001001
D
1
****
**
RET f
11f 000
D
1 1
5 (f : false)
continue : f is false
**** ****
** **
10 (f : true) RET : f is true 12 (R0,R1) (SP)M PCLr ZZ(z) (SP + 1)M PCHr SPR + 2 SPR (SP)M PCLr (SP + 1)M PCHr SPR + 2 SPR IEF2 IEF1 **** **
RETI
11101101 01001101
D
2
RETN
11101101 01000101
D
2
12
Restart
RST v
11 v 111
D
1
11
PCHr (SP-1)M PCLr (SP-2)M 0 PCHr v PCLr SPR-2 SPR
****
**
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Table 46.
I/O Instructions
Flags Addressing 7 Operation S 6 Z 42 1 0 C
Operation Name Mnemonics
Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
H P/V N
INPUT
IN A,(m)
11 011 011
D
S
2
9
(Am)1, Ar m A0~A7 Ar A8~A16
* * **
**
IN g,(C)
11 101 101 01 g 000
D
S
2
9
(BC)1 gr g = 110 : Only the flags change Cr A0~A7 Br A8~16 * RP R *
IN0 g,(m)**
11 101 101 00 g 000
D
S
3
12
(00m)g gr g = 110 : Only the flags change m A0~A7 (00) A8~A16
RP
R
(5) X XX
(6) X
IND
11 101 101 10 101 010
D
S
2
12
(BC)M (HL)M Hl2 1 Hl2 Br 1 Br Cr A0~A7
(6) X S XX X
INDR
11 101 101 10 111 010
D
S
2
14 (Br 0) 12 (BR = 0) Q
(BC)1 (HL)M HL2 1 HL8 Br-1 Br
Repeat Q until Br = 0 Cr A0~A7 Br A8 A16 (5) INI 11 101 101 10 100 010 D S 2 12 (BC)1 (HL)M HLR + 1 HLR Br-1 Br Cr A0~A7 Br A8~A16 (6) X XX (6) X
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Table 46.
I/O Instructions (Continued)
Flags Addressing 7 Operation S 6 Z 42 1 0 C
Operation Name Mnemonics
Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
H P/V N
INPUT
INIR
11 101 101 10 110 010
D
S
2
14 (Br 0) 12 (Br = 0) Q
(BC)I (HL)M HLR + 1 HLR Br-f Br
X
S
XX
X
Repeat Q until Br = 0 Cr A0~A7 Br A8 A16 OUTPUT OUT (m)A 11 010 011 S D 2 10 Ar (Am)1 m A0~A7 Ar A8~A16 OUT (C),g 11 101 101 01 g 001 S D 2 10 gr (BC)1 Cr A0~A7 Br A8~A16 OUT0(m),g** 11 101 101 00 g 001 OTDM** 11 101 101 10 001 011 S D 2 14 S D 3 13 gr (00m)1 m A0~A7 00 A8~A16 (HL)M (00C)1 HLR-1 HLR Cr-1 Cr Br-1 Br Cr A0~A7 00 A8~A16 OTDMR** 11 101 101 10 011 011 S D 2 16 (Br 0) 14 (Br = 0) Q (HL)M (00C)1 R HLR-1-HLR Cr~1 Cr Br-1 Br S RS (6) R (5) P (6) * * ** ** * * ** ** * * ** **
Repeat Q until Br = 0 Cr A0~A7 00 A8~A16 (6)
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Table 46.
I/O Instructions (Continued)
Flags Addressing 7 Operation S 6 Z 42 1 0 C
Operation Name Mnemonics
Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
H P/V N
OUTPUT OTDR
11 101 101 10 111 011
S
D
2
14 (Br 0) 12 (Br = 0) Q
(HL)M (BC)M1 X HLR-1 HLR Br-1r
S
XX
X
Repeat Q until Br = 0 Cr A0~A7 Q Br A8~A16 (HL)M (BC)M X HLR + 1 HLR (5) XX (6) X
OUTI
11 101 101 10 100 011
S
D
2
12
Br-1 Br Repeat Q until BR = 0 Cr A0~A7 Br A8~A16 OTIR 11 101 101 10 110 011 S D 2 14 (Br 0) 12 (Br = 0) Q (HL)M (BC)M X HLR + 1 HLR Br-1 Br S XX (6) X
Repeat Q until Br = 0 Cr A0~A7 Br A8~A16 TSTIOm** 11 101 101 S 01 110 100 OTIM** 11 101 101 10 000 011 S D 2 14 S 3 12 (00C)1*m Cr A0~A7 00 A8~A16 (HL)M (00C)I HLR + 1 HLR Cr + 1 Cr Br-1 Br Cr A0~A7 00 A8~A16 (6) (5) P (6) SP R R
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Table 46.
I/O Instructions (Continued)
Flags Addressing 7 Operation S 6 Z 42 1 0 C
Operation Name Mnemonics
Op Code
Immed Ext Ind Reg RegI Imp Rel Bytes States
H P/V N
OTIMR**
11 101 101 10 010 011
S
D
2
16 (Br 0) 14 (Br = 0) Q
(HL)M (00C)I R HLR + 1 HLR Cr + 1 Cr Br-1 Br
S
RS
R
Repeat Q until Br = 0 Cr A0~A7 00 A8~A16 OUTD 11 101 101 10 101 011 S D 2 12 (HL)M (BC)1 HLR-1 LR Br-1 Br Cr A0~A7 Br A8~A16 (5) Z = 1 : Br-1 = 0 Z = 0 : Br-1 0 (6) N = 1: MSB of Data = 1 N = 0 : MSB of Data = 0 X (5) XX (6) X
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Special Control Instructions
Table 47. Special Control Instructions
Flags Addressing Operation Name Mnemonics Op Code Immed Ext Ind Reg Regi Imp Rel Bytes States Operation 7642 S Z H P/V 10 NC
Special Function Carry Control
DAA
00 100 111
S/D
1
4
Decimal Adjust Accumulator C C 1 C 0 IEF1,0 IEF2 (7) 1 IEF1,1 EF2 (7) CPU halted Interrupt Mode 0
P
*
CCF SCF
00 111 111 00 110 111 11 110 011 11 111 011 01 110 110 11 101 101 01 000 110
1 1 1 1 1 2
3 3 3 3 3 6
**R * **R * **** **** **** **** **** **** **** ****
R RS ** ** ** ** ** ** ** **
CPU Control
DI EI HALT IM0
IM1
11 101 101 01 010 110
2
6
Interrupt Mode 1
IM2
11 101 101 01 011 110
2
6
Interrupt Mode 2
NOP SLP**
00 000 000 11 101 101 01 110 110
1 2
3 8
No operation Sleep
7) Interrupts are not sampled at the end of DI or EI.
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Instruction Summary
** : Added new instructions to Z80
Machine Cycles States 2 2 2 6 6 2 2 2 6 6 6 5 6 6 2 2 2 6 6 3 5 5 2 2 6 4 6 14 14 6 4 6 14 14 10 7 10 10 6 4 6 14 14 9 15 15 6 6 (If condition is false)
MNEMONICS ADC A,m ADC A,g ADC A, (HL) ADC A, (IX+d) ADC A, (IY+d) ADD A,m ADD A,g ADD A, (HL) ADD A, (IX+d) ADD A, (IY+d) ADC HL,ww ADD HL,ww ADD IX,xx ADD IY,yy AND m AND g AND (HL) AND (IX+d) AND (IY+d) BIT b, HU BIT b, (IX+d) BIT b, (IY+d) BIT b,g CALL f,mn
Bytes 2 1 1 3 3 2 1 1 3 3 2 1 2 2 2 1 1 3 3 2 4 4 2 3
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MNEMONICS
Bytes 3
Machine Cycles States 6 6 1 6 8 6 2 6 8 6 6 6 1 2 2 2 4 3 3 8 8 2 2 1 5 16 (If condition is true) 16 3 12 14 (If BC R 0 and Ar (HL) M 12 (If BC R = 0 or Ar = (HL)M 6 12 14 (If BC R 0 and Ar (HL) M 12 (If BCR = 0 or Ar = (HL) M 14 14 3 6 4 4 10 7 7 18 18 4 4 3 9 (if Br 0)
CALL mn CCF CPD CPDR
3 1 2 2 2
CP (HL) CPI CPIR
1 2 2 2
CP (IX+d) CP (IY+d) CPL CP m CP g DAA DEC (HL) DEC IX DEC IY DEC (IX+d) DEC (IY+d) DEC g DEC ww DI DJNZ j
3 3 1 2 1 1 1 2 2 3 3 1 1 1 2
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MNEMONICS EI EX AF,AF' EX DE,HL EX (SP),HL EX (SP)I,IX EX (SP),IY EXX HALT IM 0 IM 1 IM 2 INC g INC (HL) INC (IX+d) INC (IY+d) INC ww INC IX INC IY IN A,(m) IN g,(C) INI INIR IND INDR INDR IN0 g,(m)** JP f,mn
Bytes 2 1 1 1 1 2 2 1 1 2 2 2 1 1 3 3 1 2 2 2 2 2 2 2 2 2 2 3 3
Machine Cycles States 3 1 2 1 6 7 7 1 1 2 2 2 2 4 8 8 2 3 3 3 3 4 6 4 4 6 4 4 2 7 (if Br = 0) 3 4 3 16 19 19 3 3 6 6 6 4 10 18 18 4 7 7 9 9 12 14 (if Br 0) 12 (If Br = 0) 12 14 (If Br 0) 12 (If Br = 0) 12 6 (If f is false)
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MNEMONICS
Bytes 3
Machine Cycles States 3 1 2 2 3 4 2 4 2 4 2 4 2 4 2 2 2 4 2 3 4 9 (If f is true) 3 6 6 9 8 6 (If condition is false) 8 (If condition is true) 6 (if condition is false) 8 (If condition is true) 6 (If condition is false) 8 If condition is true) 6 (If condition is false) 8 (If condition is true) 6 6 6 12 6 7 12
JP (HL) JP (IX) JP (IY) JP mn JR j JR C,j
1 2 2 3 2 2 2
JR NC,j
2 2
JR Z,j
2 2
JR NZ,j
2 2
LD A, (BC) LD A, (DE) LD A,I LD A, (mn) LD A,R LD (BC),A LDD
1 1 2 3 2 1 2
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MNEMONICS LD (DE),A LD ww,mn LD ww,(mn) LDDR LD (HL),m LD HL,(mn) LD (HL),g LDI LDI,A LDIR LD IX,mn LID IX,(mn) LD (IX+d),m LD (IX+ d),g LD IY,mn LD IY,(mn) LD (IY+d),m LD (IY+d),g LD (mn),A LD (mn),ww LD (mn),HL LD (mn),IX LD (mn),IY LD R,A LD g,(HL) LD g,(IX+d) LD g,(IY+d) LD g,m
Bytes 1 3 4 2 2 2 3 1 2 2 2 2 4 4 4 3 4 4 4 3 3 4 3 4 4 2 1 3 3 2
Machine Cycles States 3 3 6 6 4 3 5 3 4 2 6 4 4 6 5 7 4 6 5 7 5 7 6 7 7 2 2 6 6 2 7 9 18 14 (If BC R 0) 12 (If BC R = 0 9 15 7 12 6 14 (If BC R 0) 12 (If BC R = 0) 12 18 15 15 12 18 15 15 13 19 16 19 19 6 6 14 14 6
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MNEMONICS LD g,g' LD SP,HL LD SP,IX LD SP,IY MLT ww" NEG NOP OR (HL) OR (IX+d) OR (IY+d) OR m OR g OTDM** OTDMR** OTDR OTIM** OTIMR** OTIR OUTD OUTI OUT (m),A OUT (C),g OUT0 (m),g ** POP IX POP IY POP zz
Bytes 1 1 2 2 2 2 1 1 3 3 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 1
Machine Cycles States 2 2 3 3 13 2 1 2 6 6 2 2 6 8 6 6 4 6 8 6 6 4 4 4 4 4 5 4 4 3 4 4 7 7 17 6 3 6 14 14 6 4 14 16 (If Br 0) 14 (If Br = 0) 14 (If Br 0) 12 (If Br = 0 14 16 (If Br 0) 14 (If Br = 0) 14 (If Br 0) 12 (If Br = 0) 12 12 10 10 13 12 12 9
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MNEMONICS PUSH IX PUSH IY PUSH zz RES b,(HL) RES b,(IX+d) RES b,(IY+d) RES b,g RET RET f
Bytes 2 2 1 2 4 4 2 1 1 1
Machine Cycles States 6 6 5 5 7 7 3 3 3 14 14 11 13 19 19 7 9 5 (If condition is false) 4 10 (If condition is true) 4 (R0, R1) 12 (R0, R1) 22 (Z) 4 12 1 3 1 3 5 13 7 19 7 19 3 7 8 16 5 13 7 19 7 19 3 7 1 3 1 3 5 13 7 19
RETI RETN RLA RLCA RLC (HL) RLC (IX-1-dl RLC (IY+d) RLC g RLD RL (HL) RL (IX+d) RL (IY+d) RL g RRA RRCA RRC (HL) RRC (IX+d)
2 10 (Z) 2 1 1 2 4 4 2 2 2 4 4 2 1 1 2 4
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MNEMONICS RRC (IY+d) RRC g RRD RR (HL) RR (IX+d) RR (IY+d) RR g RST v SBC A,(HL) SBC A, (IX+d) SBC A,(IY+d) SBC A,m SBC A,g SBC HL,ww SCF SET b,(HL) SET b,(IX+d) SET b,(IY+d) SET b,g SLA (HL) SLA (IX+d) SLA (IY+d) SLA g SLP** SRA (HL) SRA (IX+d) SRA (IY+d) SRA g SRL (HL) SRL (IX+d)
Bytes 4 2 2 2 4 4 2 1 1 3 3 2 1 2 1 2 4 4 2 2 4 4 2 2 2 4 4 2 2 4
Machine Cycles States 7 3 8 5 7 7 3 5 2 6 6 2 2 6 1 5 7 7 3 5 7 7 3 2 5 7 7 3 5 7 19 7 16 13 19 19 7 11 6 14 14 6 4 10 3 13 19 19 7 13 19 19 7 8 13 19 19 7 13 19
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MNEMONICS SRL (IY+d) SRL g SUB (HL) SUB (IX+d) SUB (IY+d) SUB m SUB g **TSTIO m **TST g TST m** TST (HL)** XOR (HL) XOR (IX+d) XOR (IY+d) XOR m XOR g
Bytes 4 2 1 3 3 2 1 3 2 3 2 1 3 3 2 1
Machine Cycles States 7 3 2 6 6 2 2 4 3 3 4 2 6 6 2 2 19 7 6 14 14 6 4 12 7 9 10 6 14 14 6 4
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Op Code Map
Table 48. 1st Op Code Map Instruction Format: XX
ww (L0 = ALL) BC DE HL SP L0 = 0~7 BC NZ H 0010 2 (HL) 0011 3 JR NC,j LD g, s LD (mn) ,HL LD (mn), A B 0100 4 D H (HL) 1000 8 1001 9 1010 A 1011 B 00H 1100 C RET f POP zz JP f, mn DE NC 10H 1101 D HL P0 20H 1110 E AF P 30H 1111 F 0 1 2 zz f v
g (LO = 0~7) B D 0001 1
HI L O
B C D 0000 0001 0010 0 1 2
0000 0 N0P
0101 0110 0111 5 6 7 note 1)
DJNZj JR NZ,j
LD ww, mn LD (ww), A
ADD A,s
SUB s AND s OR s
E H L
0011 0100 0101
3 4 5 6 7 8 9
INC ww INC g DEC g LD g,m RLCA RLA note1 note1 note1 note2 DAA SCF JR Z,j JR C,j HALT note2 note2 note2 note2
JP mn OUT (m),A CALL f, mn PUSH zz ADD A,m RST v RET f SUB m
EX(SP), DI HL
3 4 5
(HL) 0110 S (HI = ALL) A B 0111 1000 1001
AND m OR m 6 7 8
EXAF,A JR j F' ADD HL, ww
C
RET LD g, s ADC A,s SBC A,s XOR s CP s JP f, mn
EXX
JP(HL)
LD SP, HL
9
D
1010
A
LD A,(ww)
LD HL, (mn)
LD A, (mn)
A
E H L
1011 1100 1101
B C D E F
DEC ww INC g DEC g LD g,m RRCA 0 C RRA 1 E CPL 2 L CCF 3 A 4 C 5 E 6 L 7 A 8 9 A B note2 note2 note2 note2 note2
Table2 IN A(m) EXDE,H EI L CALL f, mn CALL note3 mn ADC A,m RST v C Z 08H D C 18H E PE 28H F M 3BH Table3
B C
note3 D CP m E F
(HL) 1110 A 1111
SBC A,m XOR m
f v
g(L0 = 8~F)
LO = 8~F
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Note 1: (HL) replaces g. Note 2: (HL) replaces s. Note 3: If DDH is supplemented as first Op Code for the instructions which have HL or (HL) as an operand in Table 48, the instructions are executed replacing HL with IX and (HL) with (IX+d). ex. 22H : LD (mn), HL DDH 22H : LD (mn), IX If FDH is supplemented as 1st Op Code for the instructions which have HL or (HL) as an operand in Table 48, the instructions are executed replacing HL with IY and (HL) with (IY+d). ex. 34H : INC (HL)
FDH 34H : INC (IY+d)
However, JP (HL) and EX DE, HL are exceptions and note the following.
* * *
If DDH is supplemented as 1st Op Code for JP (HL), (IX) replaces (HL) as operand and JP (IX) is executed If FDH is supplemented as 1st Op Code for JP (HL), (IY) replaces (HL) as operand and JP (IY) is executed Even if DDH or FDH is supplemented as 1st Op Code for EX DE, HL, HL is not replaced and the instruction is regarded as illegal instruction.
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Table 49.
2nd Op Code Map Instruction Format: CB XX
b (L0 = 0~7) 0 2 0101 5 4 0110 6 6 0111 7 0 1000 8 2 1001 9 4 1010 A 6 1011 B 0 1100 C 2 1101 D 4 1110 E 6 1111 F 0 1 RLC g RL g SLA g 2 3 BIT b,g RES b,g SET b,g 4 5 NOTE NOTE NOTE 1) 1) 1) NOTE1) NOTE1) NOTE1) 6 7 8 RRC g RR g SRA g SRL g BIT b,g RES b,g SET b,g 9 A B C D NOTE NOTE NOTE NOTE NOTE1) 1) 1) 1) 1) NOTE1) NOTE 1) E F 0 1 2 3 4 1 5 3 6 5 7 7 8 1 9 3 A 5 B 7 C 1 D 3 E 5 F 7
H I 0000 L O
B C D E H L 0000 0001 0010 0011 0100 0101 0 1 2 3 4 5 6 7 8 9 A B C D E F 0
0001 1
0010 2
0011 3
0100 4
g (HI = ALL)
(HL 0110 ) A B C D E H L 0111 1000 1001 1010 1011 1100 1101
(HL 1110 ) A 1111
b (LO = 8 ~ F)
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Table 50.
2nd Op Code Map Instruction Format: ED XX
ww (L0 = ALL) BC G (L0 = 0~7) B D 0001 1 H 0010 2 0011 3 B 0100 4 D 0101 5 H 0110 6 0111 7 1000 8 1001 9 1010 A LDI CPI INI OTIM OTIM OUTI R TST m TSTIO m 1011 B LDIR CPIR INIR OTIR 1100 C 1101 D 1110 E 1111 F 0 1 2 3 4 5 IM 1 RRD LDD CPD IND OTD M OTD MR LDDR CPDR INDR SLP 6 7 8 9 A B C D IM 2 LDR, A 0 C 1 E 2 L 3 A 4 C LD A,R 5 E RLD 6 L 7 A 8 9 A B C D E F E F DE HL SP
H I 0000 L O
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F TST g TST g 0
IN0 g, (m) OUT0 (m),g
IN g, (C) OUT (C),g SBC HL, ww LD (mn), ww TST (HL) NEG RETN IM 0
LD I,A LD A,I IN0 g, (m) OUT0 (m), g IN g, (C) OUT (C) , g ADC HL,ww LD ww, (mn) MLT ww RETI
OUTD OTDR
g (L0 = 8~F)
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Bus Control Signal Conditions
BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE
* (ADDRESS) invalid Z (DATA) high impedance. ** added new instructions to Z80
Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle
Machine Cycle States MC1 Address Data 1st Op Code Z 1st Op Code 2nd Op Code Z 1st Op Code 2nd Op Code Z RD 0 1 0 0 1 0 0 1 WR MREQ 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1
T1T2T3 1st Op Code Address TiTiTiTi * T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address TiTiTiTi * T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address TiTiTiTi *
ADD HL,ww
MC2 ~MC5 MC1
ADD IX,xx ADD IY,yy
MC2 MC3 ~MC6 MC1
ADC HL,ww SBC HL,ww
MC2 MC3 ~MC6
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Table 51.
Instruction ADD A,g ADC A,g SUB g SBC A,g AND g OR g XOR g CP g ADD A,m ADC A,m SUB m SBC A,m AND m OR m XOR m CP m ADD A, (HL) ADC A, (HL) SUB (HL) SBC A, (HL) AND HU OR (HL) XOR (HL) CP (HL)
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code Z RD 0 1 WR MREQ 1 1 0 1 IORQ M1 HALT ST 1 1 0 1 1 1 0 1
T1T2T3 1st Op Code Address Ti *
MC1 MC2
T1T2T3 1st Op Code Address T1T2T3 1st operand Address
1st Op Code m
0 0
1 1
0 0
1 1
0 1
1 1
0 1
MC1 MC2
T1T2T3 1st Op Code Address T1T2T3 HL
1st Op Code DATA
0 0
1 1
0 0
1 1
0 1
1 1
0 1
ADD A, (IX+ d) ADD A, (IY+d) ADC A, (IX+d) ADC A, (IY+d) SUB (lX+d) SUB (IY+d) SBC A, (IX+ d) SBC A, (IY+ d) AND (IX+d)
MC1 MC2
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address
1st Op Code 2nd Op Code
0 0
1 1
0 0
1 1
0 0
1 1
0 1
MC3
T1T2T3 1st operand Address
d
0
1
0
1
1
1
1
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Table 51.
Instruction AND (IY+ d) OR (IX + d) OR (IY+d) XOR (IX + d) XOR (IY+d) CP (IX+d) CP (IY+d)
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC4 ~MC6 TiTiTi Address * Data Z RD 1 WR MREQ 1 1 IORQ M1 HALT ST 1 1 1 1
MC6 MC1
T1T2T3 IX+d IY+d T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 3rd Op Code Address T1T2T3 IX+ d IY+d
DATA 1st Op Code 2nd Op Code 1st Op Code 2nd Op Code DATA 1st Op Code 2nd Op Code d 3rd Op Code DATA
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 1 0 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1
1 0 1 0 1 1 0 1 1 1 1
BIT b,g
MC2 MC1
BIT b, (HL)
MC2 MC3 MC1 MC2
BIT b, (IX+d) BIT b, (IY+d)
MC3 MC4 MC5
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code n m Z PCH PCL 1st Op Code n 1st Op Code n m Z PCH PCL 1st Op Code RD 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 WR MREQ 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
CALL mn
MC3 MC4 MC5 MC6
T1T2T3 SP-1 T1T2T3 SP-2 T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
CALL f,mn (If MC1 condition is false) MC2 MC1 MC2 CALL f,mn if condition is true) MC3 MC4 MC5 MC6 CCF MC1
T1T2T3 SP-1 T1T2T3 SP-2 T1T2T3 1st Op Code Address
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC4 ~MC6 MC1 Address Data 1st Op Code 2nd Op Code DATA Z 1st Op Code 2nd Op Code DATA Z 1st Op Code 2nd Op Code DATA Z 1st Op Code 1st Op Code Z 1st Op Code RD 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 WR MREQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 0 1 0
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL TiTiTi *
CPI CPD
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL TiTiTi TiTi *
CPIR CPDR (If BC R 0 and Ar = (HL)M )
MC2 MC3 MC4~M C8 MC1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL TiTiTi *
CPIR CPDR (If BC R=0 or Ar=(HL)M )
MC2 MC3 MC4~M C6
CPL
MC1 MC1
T1T2T3 1st Op Code Address T1T2T3 1st Op Code Address Ti *
DAA MC2 DI*1 MC1
T1T2T3 1st Op Code Address
* 1 Interrupt request is not sampled.
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 Address Data 1st Op Code Z j-2 Z 1st Op Code Z j-2 1st Op Code 1st Op Code 1st Op Code Z 1st Op Code DATA DATA Z H L RD 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 1 1 WR MREQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1
T1T2T3 1st Op Code Address Ti*2 *
DJNZ j (If Br 0)
MC2 MC3 MC4~M C5 MC1
T1T2T3 1st operand Address TiTi *
T1T2T3 1st Op Code Address Ti*1 *
DJNZ j (If Br=0)
MC2 MC3
T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 1st Op Code Address T1T2T3 1st Op Code Address Ti *
EI*3 EX DE, HL EXX EX AF, AF'
MC1 MC1 MC1 MC2 MC1 MC2 MC3 MC4 MC5 MC6
T1T2T3 1st Op Code Address T1T2T3 SP T1T2T3 SP+1 Ti *
EX (SP), HL
T1T2T3 SP+1 T1T2T3 SP
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored) *3 Interrupt request is not sampled.
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC4 MC5 MC6 MC7 MC1 Address Data 1st Op Code 2nd Op Code DATA DATA Z IXH IYH IXL IYL 1st Op Code RD 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 1 1 WR MREQ 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 SP T1T2T3 SP+1 Ti *
EX (SP),IX EX (SP),IY
T1T2T3 SP+1 T1T2T3 SP T1T2T3 1st Op Code Address --
HALT
-- MC1 MC2 MC1
Next Op Code Next Op Address Code 1st Op Code 2nd Op Code 1st Op Code Z 1st Op Code DATA Z DATA
IM0 IM1 IM2
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st Op Code Address Ti *
INC g DEC g
MC2 MC1
T1T2T3 1st Op Code Address T1T2T3 HL Ti *
INC (HL) DEC (HL)
MC2 MC3 MC4
T1T2T3 HL
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC4~M C5 MC6 MC7 MC8 MC1 Address Data 1st Op Code 2nd Op Code d Z DATA Z DATA 1st Op Code Z 1st Op Code 2nd Op Code Z 1st Op Code m RD 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 WR MREQ 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 0 t 0 0 1 0 0 1 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address TiTi *
INC (IX+ d) INC (IY+d)
DEC (IX+d) DEC (IY+d)
T1T2T3 X+ d IY+ d T1 *
T1T2T3 IX+ d IY+d T1T2T3 1st Op Code Address Ti *
INC ww DEC ww
MC2 MC1
INC IX INC IY DEC IX DEC IY
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
MC2 MC3 MC1 MC2 MC3
T1T2T3 1st Op Code Address T1T2T3 1st operand Address
IN A,(m)
T1T2T3 m to A0~A7 DATA A to A8~A15
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC1 MC2 Address Data 1st Op Code 2nd Op Code DATA 1st Op Code 2nd Op Code m DATA RD 0 0 0 0 0 0 0 WR MREQ 1 1 1 1 1 1 1 0 0 1 0 0 0 1 IORQ M1 HALT ST 1 1 0 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 BC T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 m to A0~A7 00H to A8~A15 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 BC T1T2T3 HL T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 BC T1T2T3 HL TiTi *
IN g,(C)
INO g,(m)** MC3 MC4
MC1 MC2 MC3 MC4 MC1 MC2 INIR INDR (If Br0) MC3 MC4 MC5~M C6
1st Op Code 2nd Op Code DATA DATA 1st Op Code 2nd Op Code DATA DATA Z
0 0 0 1 0 0 0 1 1
1 1 1 0 1 1 1 0 1
0 0 1 0 0 0 1 0 1
1 1 0 1 1 1 0 1 1
0 0 1 1 0 0 1 1 1
1 1 1 1 1 1 1 1 1
0 1 1 1 0 1 1 1 1
INI IND
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 Address Data 1st Op Code 2nd Op Code DATA DATA 1st Op Code n m 1st Op Code n 1st Op Code n m 1st Op Code 1st Op Code 2nd Op Code RD 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 WR MREQ 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 IORQ M1 HALT ST 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 0 0 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 BC T1T2T3 HL T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 1st Op Code Address T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address
INIR INDR (If Br=0)
MC2 MC3 MC4 MC1 MC2 MC3 MC1
JP mn
JP f,mn (if is false)
MC2 MC1
JP f,mn (If f is true)
MC2 MC3
JP (HL)
MC1 MC1
JP (IX) JP (IY)
MC2
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3~M C4 Address Data 1st Op Code j-2 Z 1st Op Code j-2 1st Op Code j-2 Z 1st Op Code Z 1st Op Code m 1st Op Code DATA RD 0 0 1 0 0 0 0 1 0 1 0 0 0 0 WR MREQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address TiTi *
JR j
JR C,j JR NC,j JR Z,j JR NZ,j (if condition is false)
MC1 MC2 MC1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 1st operand Address TiTi *
JR C,j JR NC,j JR Z,j JR NZ,j (if condition is true)
MC2 MC3~M C4 MC1
LD g,g' MC2 MC1 LD g,m MC2 MC1 LD g, (HL) MC2
T1T2T3 1st Op Code Address Ti *
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 HL
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code d Z DATA 1st Op Code Z g 1st Op Code 2nd Op Code d Z g 1st Op Code m DATA RD 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 WR MREQ 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address TiTi *
LD g, (IX+d) LD g, (IY+d)
MC3 MC4~M C5 MC6 MC1
T1T2T3 IX+d IY+d T1T2T3 1st Op Code Address Ti *
LD (HL),g
MC2 MC3 MC1 MC2
T1T2T3 HL T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address TiTiTi *
LD (IX + d),g LD (IY + d),g
MC3 MC4~ MC6 MC7 MC1
T1T2T3 IX+d IY+d T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 HL
LD (HL),m
MC2 MC3
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code d m DATA 1st Op Code DATA 1st Op Code n m DATA 1st Op Code Z A RD 0 0 0 0 1 0 0 0 0 0 0 0 1 1 WR MREQ 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 IX+ d IY+d T1T2T3 1st Op Code Address T1T2T3 BC DE T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 mn T1T2T3 1st Op Code Address Ti *
LD (IX+d),m LD (IY+d),m
MC3 MC4 MC5 MC1
LD A, (BC) LD A, (DE)
MC2 MC1 MC2 MC3 MC4 MC1
LD A,(mn)
LD (BC),A LD (DE),A
MC2 MC3
T1T2T3 BC DE
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code n m Z A 1st Op Code 2nd Op Code 1st Op Code n m 1st Op Code 2nd Op Code n m RD 0 0 0 1 1 0 0 0 0 0 0 0 0 0 WR MREQ 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
LD (mn),A MC3 MC4 MC5 LD A,I LD A,R LD I,A LD R,A *4 MC1 MC2 MC1 LD ww, mn MC2 MC3 MC1 MC2 MC3 MC4
T1T2T3 mn T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address
LD IX,mn LD IY,mn
*4 In the case of R1 and Z MASK, interrupt request is not sampled.
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code n m DATA DATA 1st Op Code 2nd Op Code n m DATA DATA 1st Op Code 2nd Op Code n m DATA DATA RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR MREQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 mn T1T2T3 mn+1 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 mn T1T2T3 mn+ 1 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address T1T2T3 mn T1T2T3 mn+1
LD HL, (mn) MC3 MC4 MC5 MC1 MC2 LD ww,(mn) MC3 MC4 MC5 MC6 MC1 MC2 LD IX,(mn) LD IY,(mn) MC3 MC4 MC5 MC6
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code n m Z L H 1st Op Code 2nd Op Code n m Z wwL wwH RD 0 0 0 1 1 1 0 0 0 0 1 1 1 WR MREQ 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
LD (mn),HL MC3 MC4 MC5 MC6 MC1 MC2 MC3 LD (mn),ww MC4 MC5 MC6 MC7
T1T2T3 mn T1T2T3 mn+1 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
T1T2T3 mn T1T2T3 mn+1
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 Address Data 1st Op Code 2nd Op Code n m Z IXL IYL IXH IYH 1st Op Code Z 1st Op Code 2nd Op Code Z 1st Op Code 2nd Op Code DATA DATA RD 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 1 WR MREQ 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 2nd operand Address Ti *
LD (mn),IX LD (mn),IY MC4 MC5 MC6 MC7 MC1 LD SP, HL MC2 MC1 LD SP,IX LD SP,IY MC2 MC3 MC1 LDI LDD MC2 MC3 MC4
T1T2T3 mn T1T2T3 mn+1 T1T2T3 1st Op Code Address Ti *
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 DE
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC4 MC5~M C6 MC1 Address Data 1st Op Code 2nd Op Code DATA DATA Z 1st Op Code 2nd Op Code DATA DATA 1st Op Code 2nd Op Code Z RD 0 0 0 1 1 0 0 0 1 0 0 1 WR MREQ 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 DE TiTi *
LDIR LDDR (If BCR0)
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 DE T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address TiTiTTi * TiTiTiTi TiTiTi T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st Op Code Address
LDIR LDDR (If BCR=0)
MC2 MC3 MC4 MC1 MC2 MC3 ~MC13 MC1
MLT ww**
NEG MC2 NOP MC1
1st Op Code 2nd Op Code 1st Op Code
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 1 0
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 MC4 MC1 MC2 MC3 MC4 MC1 MC2 Address Data 1st Op Code m Z RD 0 0 1 1 0 0 1 1 0 0 0 1 1 WR MREQ 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 IORQ M1 HALT ST 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 1st operand Address Ti *
OUT (m),A
T1T2T3 m to A0~A7 A A to A8~A15 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti * 1st Op Code 2nd Op Code Z g 1st Op Code 2nd Op Code m Z g
OUT (C),g
T1T2T3 BC T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address Ti *
OUT0 (m),g** MC3 MC4 MC5
T1T2T3 m to A0~A7 00H to A8~A15
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code Z DATA DATA RD 0 0 1 0 1 WR MREQ 1 1 1 1 0 0 0 1 0 1 IORQ M1 HALT ST 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
OTIM** OTDM**
MC3 MC4 MC5
T1T2T3 HL T1T2T3 C to A0~A7 00H to A8~A15 Ti *
MC6 MC1 MC2 OTIMR** OTDMR** (If Br0) MC3 MC4 MC5
Z 1st Op Code 2nd Op Code Z DATA DATA
1 0 0 1 0 1
1 1 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 0
1 0 0 1 1 1
1 1 1 1 1 1
1 0 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
T1T2T3 HL T1T2T3 C to A0~A7 00H to A8~A15 TiTiTi *
MC6~M C8
Z
1
1
1
1
1
1
1
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code Z DATA DATA RD 0 0 1 0 1 WR MREQ 1 1 1 1 0 0 0 1 0 1 IORQ M1 HALT ST 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
OTIMR** OTDMR** (if Br= 0)
MC3 MC4 MC5
T1T2T3 HL T1T2T3 C to A0~A7 00H to A8~A15 Ti *
MC6 MC1 OUTI OUTD MC2 MC3 MC4 MC1 MC2 MC3 MC4 MC5~M C6
Z 1st Op Code 2nd Op Code DATA DATA 1st Op Code 2nd Op Code DATA DATA Z
1 0 0 0 1 0 0 0 1 1
1 1 1 1 0 1 1 1 0 1
1 0 0 0 1 0 0 0 1 1
1 1 1 1 0 1 1 1 0 1
1 0 0 1 1 0 0 1 1 1
1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 0 1 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 BC T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 BC TiTi *
OTIR OTDR (If Br 0)
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 Address Data 1st Op Code 2nd Op Code DATA DATA 1st Op Code DATA DATA 1st Op Code 2nd Op Code DATA DATA 1st Op Code Z zzH zzL RD 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 WR MREQ 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 IORQ M1 HALT ST 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL T1T2T3 BC T1T2T3 1st Op Code Address T1T2T3 SP T1T2T3 SP+1 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 SP T1T2T3 SP+1 T1T2T3 1st Op Code Address TiTi *
OTIR OTDR (if Br=0)
MC2 MC3 MC4 MC1
POP zz
MC2 MC3 MC1
POP IX POP IY
MC2 MC3 MC4
PUSH zz
MC1 MC2 ~MC3 MC4 MC5
T1T2T3 SP-1 T1T2T3 SP-2
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code Z IXH IYH IXL IYL 1st Op Code DATA DATA 1st Op Code Z 1st Op Code Z DATA DATA 1st Op Code 2nd Op Code DATA DATA RD 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 WR MREQ 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address TiTi *
PUSH IX PUSH IY
MC3~M C4 MC5 MC6 MC1
T1T2T3 SP-1 T1T2T3 SP-2 T1T2T3 1st Op Code Address T1T2T3 SP T1T2T3 SP+1 T1T2T3 1st Op Code Address TiTi *
RET
MC2 MC3 MC1
RET f (If condition is false)
MC2~M C3 MC1
T1T2T3 1st Op Code Address Ti *
RET f (If condition is true)
MC2 MC3 MC4 MC1 MC2 MC3 MC4
T1T2T3 SP T1T2T3 SP+1 T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 SP T1T2T3 SP+1
RETI (R0, R1) RETN
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 MC3 ~MC5 MC6 Address Data 1st Op Code 2nd Op Code Z 1st Op Code Z 2nd Op Code data data 1st Op Code RD 0 0 1 0 1 0 0 0 0 WR MREQ 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 0*5 1 1 0*5 1 1 1*5 1 1 0*5 1 0 1*5 1 1 0*5 1 0 1*5 1 1 1*5 1 1 0 1 0 1 1 1 1 1 1 1 0
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address TiTiTi *
RETI (Z) MC7 MC8 MC9 MC10 RLCA RLA RRCA RRA RLC g RL g RRC g RR g SLA g SRA g SRL g MC1
T1T2T3 1st Op Code Address Ti *
T1T2T3 2nd Op Code Address T1T2T3 SP T1T2T3 SP+1 T1T2T3 1st Op Code Address
MC1 MC2 MC3
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
1st Op Code 2nd Op Code Z
0 0 1
1 1 1
0 0 1
1 1 1
0 0 1
1 1 1
0 1 1
*5 The upper and lower data show the state of M1 when IOC = 1 and IOC = 0 respectively.
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 Address Data 1st Op Code 2nd Op Code DATA Z DATA 1st Op Code 2ndOp Code d 3rd Op Code DATA Z DATA 1st Op Code 2nd Op Code DATA Z DATA RD 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 WR MREQ 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1
RLC (HL) RL (HL) RRC (HL) RR (HL) SLA (HL) SRA (HL) SRL (HL)
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL Ti *
MC2 MC3 MC4 MC5
T1T2T3 HL T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 3rd Op Code Address T1T2T3 IX+d IY+d Ti *
RLC (IX + d) RLC (IY + d) RL (IX + d) RL (IY + d) RRC (IX + d) RRC (IY + d) RR (IX + d) RR (IY + d) SLA (IX + d) SLA (IY + d) SRA (IX + d) SRA (IY + d) SRL (IX + d) SRL (IY + d)
MC1 MC2 MC3 MC4 MC5 MC6 MC7 MC1 MC2
T1T2T3 IX+d IY+d T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL TiTiTiTi * T1T2T3 HL
RLD RRD
MC3 MC4~M C7 MC8
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 ~MC3 MC4 MC5 Address Data 1st Op Code Z PCH PCL 1st Op Code 1st Op Code 2nd Op Code Z 1st Op Code 2ndOp Code DATA Z DATA RD 0 1 1 1 0 0 0 1 0 0 0 1 1 WR MREQ 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1
T1T2T3 1st Op Code Address TiTi *
RST v
T1T2T3 SP-1 T1T2T3 SP-2 T1T2T3 1st Op Code Address T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
SCF
MC1 MC1
SET b,g RES b,g
MC2 MC3 MC1 MC2 MC3 MC4 MC5
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 HL Ti *
SET b. (HL) RES b, (HL)
T1T2T3 HL
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 MC2 Address Data 1st Op Code 2nd Op Code d 3rd Op Code DATA Z DATA 1stOp Code 2nd Op Code Z 1st Op Code 2nd Op Code m DATA RD 0 0 0 0 0 1 1 0 0 1 0 0 0 0 WR MREQ 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 IORQ M1 HALT ST 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 3rd Op Code Address T1T2T3 IX+d IY+d Ti *
SET b, (IX+d) SET b, (IY+d) RES b, (IX+d) RES b, (IY+d)
MC3 MC4 MC5 MC6 MC7 MC1
T1T2T3 IX+ d IY+d T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address -- 7FFFFH
SLP**
MC2 -- MC1 MC2
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 C to A0~A7 00H to A8~A15
TSTIO m** MC3 MC4
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Table 51.
Instruction
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine Cycle States MC1 Address Data 1st Op Code 2nd Op Code Z 1st Op Code 2nd Op Code m 1st Op Code 2nd Op Code Z Data RD 0 0 1 0 0 0 0 0 1 0 WR MREQ 1 1 1 1 1 1 2 1 1 1 0 0 1 0 0 0 0 0 1 0 IORQ M1 HALT ST 1 1 1 1 1 1 2 1 1 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 2 1 1 1 0 1 1 0 1 1 0 1 1 1
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti *
TST g**
MC2 MC3 MC1 MC2 MC3
T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address T1T2T3 1st operand Address T1T2T3 1st Op Code Address T1T2T3 2nd Op Code Address Ti T1T23 * HL
TST m**
TST (HL)**
MC1 MC2 MC3 MC4
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INTERRUPTS
Table 52.
Instruction Machine Cycle States MC1 T1T2T3
Interrupts
Address Next Op Code Address (PC) * SP-1 SP-2 Next Op Code Address * SP-1 SP-2 Z PCH PCL 1st (PC) Op Code Z PCH PCL Data RD WR MREQ IORQ M1 HALT ST 0 1 0 1 0 1 0
NMI
MC2 ~MC3 MC4 MC5 MC1
T1T1 T1T2T3 T1T2T3 T1T2TW TWT3 T1T1 T1T2T3 T1T2T3 T1T2Tw TWT3 T1T2T3 T1T2T3 Ti T1T2T3 T1T2T3 T1T2TW TWT3 T1T2T3 T1T2T3
1 1 1 1
1 0 0 1
1 0 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 0
INT0 Mode 0 (RST Inserted)
MC2 ~MC3 MC4 MC5 MC1
1 1 1 1
1 0 0 1
1 0 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 0
1st Next Op Op Code Code Address (PC) PC PC+1 * SP-1 SP-2 Next Op Code Address (PC) SP-1 SP-2 PCH PCL n m Z PC+2(H) PC+2(L)
INT0 Mode 0 (Call Inserted)
MC2 MC3 MC4 MC5 MC6 MC1
0 0 1 1 1 1
1 1 1 0 0 1
0 0 1 0 0 1
1 1 1 1 1 0
1 1 1 1 1 0
1 1 1 1 1 1
1 1 1 1 1 0
INT0 Mode 1 MC2 MC3
1 1
0 0
0 0
1 1
1 1
1 1
1 1
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Table 52.
Instruction Machine Cycle States MC1
Interrupts (Continued)
Address Data RD WR MREQ IORQ M1 HALT ST 1 1 1 0 0 1 0
T1T2TW TWT3 Ti T1T2T3 T1T2T3 T1T2T3 T1T2T3 T1T2,TW T1T2,TW TWT3 Ti T1T2T3 T1T2T3 T1T2T3 T1T2T3
Next Vector Op Code Address (PC) * SP-1 SP-2 I, Vector I, Vector+1 Next Op Code Address (PC) * SP-1 SP-2 I, Vector I, Vector+1 Z PCH PCL DATA DATA Z PCH PCL DATA DATA
INT0 Mode 2
MC2 MC3 MC4 MC5 MC6 MC1
1 1 1 0 0 1
1 0 0 1 1 1
1 0 0 0 0 1
1 1 1 1 1 1
1 1 1 1 1 1
1
1 1
1 1 1 1
1 1 1 0
INT1 INT2 Internal Interrupts
MC2 MC3 MC4 MC5 MC6
1 1 1 0 0
1 0 0 1 1
1 0 0 0 0
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
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Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Table 53.
Current Normal Status Operation (CPU mode and IOSTOP Request Mode) WAIT Refresh Request Request of Refresh by the on-chip Refresh Controller DREQ0 DREQ1 Acceptable
Request Acceptances in Each Operating Mode
WAIT State Acceptable
Refresh Cycle Not acceptable Not acceptable
Interrupt Acknowledge Cycle Acceptable Refresh cycle begins at the end MC Acceptable DMA cycle begins at the end of MC.
DMA Cycle Acceptable
BUS RELEASE SLEEP Mode Mode Not acceptable Not acceptable Not acceptable
SYSTEM STOP Mode Not acceptable Not acceptable
Refresh cycle Not begins at the acceptable end of Machine Cycle (MC) DMA cycle begins at the end of MC DMA cycle begins at the end of MC
Refresh cycle Not begins at the acceptable end of MC Acceptable Refer to "DMA Controller" for details.
Acceptable Refresh cycle precedes. DMA cycle begins at the end of one MC Not acceptable
Acceptable Not *After BUS acceptable RELEASE cycle, DMA cycle begins at the end of one MC Acceptable
Not acceptable
BUSREQ
Bus is released Not at the end of acceptable MC Accepted after executing the current instruction.
Bus is released at the end of MC Not acceptable
Bus is Continue released at the BUS end of MC RELEASE mode Not acceptable Not acceptable
Acceptable
Interrupt INT0, INT1, 1NT2
Accepted Not after acceptable executing the current instruction
Acceptable Return from SLEEP mode to normal operation.
Acceptable Return from SYSTEM STOP mode to normal operation
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Table 53.
Current Normal Status Operation (CPU mode and IOSTOP Mode) Request Internal I/O Interrupt NMI
Request Acceptances in Each Operating Mode
WAIT State
Refresh Cycle
Interrupt Acknowledge Cycle
DMA Cycle
BUS RELEASE SLEEP Mode Mode
SYSTEM STOP Mode Not acceptable Acceptable Return from SYSTEM STOP mode to normal operation
Not acceptable Acceptable Interrupt DMA cycle acknowledge stops cycle precedes. NMI is accepted after executing
Note: * Not acceptable when DMA Request is in level-sense. : Same as above. MC: Machine Cycle
REQUEST PRIORITY
The Z80180 features three types of requests.
.
Table 54. The Z80180 Types of Requests
Type 1 Type 2 Type 3 Accepted in specified state Accepted in each machine cycle Accepted in each instruction WAIT Refresh Request, DMA Request, and Bus Request. Interrupt Request
Type 1, Type 2, and Type 3 requests priority as follows.
* *
Highest priority Type 1 > Type 2 > Type 3 lowest priority Each request priority in Type 2 is shown as follows. highest priority Bus Req. > Refresh Req. > DMA Request lowest priority
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Note: If Bus Request and Refresh Request occur simultaneously, Bus Request is accepted but Refresh Request is cleared.
OPERATION MODE TRANSITION
NORMAL *1
0 T= SE RE 0 T= SE RE
HAL T In stru ctio n Inte rru pt
RESET
RESET = 0
P SL on cti tru t Ins up err Int
HALT
RE SE T=
0
SYSTEM STOP
RESET = 0
S RE
SL PI
ET
I nte rru pt nst ruc tion
=0
IOSTOP
IOSTOP = 0
IOSTOP = 1
SLEEP
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NORMAL *1
RE T SE =0
DM A En
RESET
1 T= SE RE RESET = 0
End
Re que st * 2 do fD MA *3
DMA
H ES FR RE uest Req
RE S
E of R
=1
=0
=0
ET
FRE
REQ
B US
BUS RELEASE
REFRESH
Figure 94.
Operation Mode Transition
* 1. NORMAL: CPU executes instructions normally in NORMAL mode. * 2. DMA request: DMA is requested in the following cases. - DREQ0, DREQ1 = 0 memory to/from (memory mapped) I/0 DMA transfer - b. DEO = 1 (memory to/from memory DMA transfer) * 3. DMA end: DMA ends in the following cases:
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B
RE US
EQ SR BU
=1
of R
Q
=0
REF R Req E SH ues t
EF R E SH
RE Q
BUS
RES ET =0
SH
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-
- -
DREQ0, DREQ1 = 1 memory to/from (memory mapped) I/O DMA transfer BCR0, BCR1 = 0000H (all DMA transfers) NMI = 0 (all DMA transfers)
OTHER OPERATION MODE TRANSITIONS
The following operation mode transitions are also possible.
1. HALT
IOSTOP
{ {
DMA REFRESH BUS RELEASE DMA REFRESH BUS RELEASE BUS RELEASE BUS RELEASE
} }
2.
SLEEP SYSTEM STOP
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Status Signals
PIN OUTPUTS IN EACH OPERATING MODE
Table 55 describes pin outputs in each operating mode.
Table 55.
Mode CPU Operation Op Code Fetch (1st Op Code) Op Code Fetch (except 1 st Op Code) MemRead Memory Write I/O Read I/O Write Internal Operation Refresh Interrupt Acknowledge Cycle (1st Machine Cycle) NMI INT0 INT1, INT2 & Internal Interrupts
Pin Outputs in Each Operating Mode
M1 MREQ IORQ RD WR RFSH HALT BUSACK ST 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 Address Data BUS BUS A A IN IN
1 1 1 1 1 1 0 0 1
0 0 1 1 1 0 0 1 1
1 1 0 0 1 1 1 0 1
0 1 0 1 1 1 0 1 1
1 0 1 0 1 1 1 1 1
1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 1 1 * 0 0 0
A A A A A A A A A
IN OUT IN OUT IN IN IN IN IN
BUS RELEASE HALT SLEEP
1 0 1
Z 0 1
Z 1 1
Z 0 1
Z 1 1
1 1 1
1 0 0
0 1 1
* 0 1
Z A 1
IN IN IN
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Table 55.
Mode
Pin Outputs in Each Operating Mode (Continued)
M1 MREQ IORQ RD WR RFSH HALT BUSACK ST Memory Read 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 * * * * 1 1 1 1 1 1 0 0 0 0 1 Address Data BUS BUS A A A A Z IN OUT IN OUT IN
Internal DMA
Memory Write I/O Read I/O Write
RESET
* * * * * * *
PIN STATUS
1 : High 0 : Low A : Programmable Z : High Impedance IN : Input OUT : Output * : Invalid
Tables 56 describes the status of each ping during RESET and LOW POWER OPERATION modes.
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Table 56.
Pin Status During RESET and LOW POWER OPERATION Modes Pin Status in Each Operation Mode SYSTEM STOP IN (N) OUT IN (A) IN (A) IN (A) IN (A) IN (A) IN (A) 1 1 1 H Z H N (N) IN (N) H IN (N) Z
Symbol WAIT BUSACK BUSREQ RESET NMI INT0 INT1 INT2 ST A0-A17, A19 A18/TOUT
Pin Function -- -- -- -- -- -- -- -- -- -- A18 TOUT
RESET IN (N) 1 IN (N) 0 IN (N) IN (N) IN (N) IN (N) 1 Z Z Z Z 1 IN (N) IN (N) 1 IN (N) Z
SLEEP IN (N) OUT IN (A) IN (A) IN (A) IN (A) IN (A) IN (A) 1 1 1 OUT Z H IN (A) IN (A) OUT IN (A) OUT
IOSTOP IN (A) OUT IN (A) IN (A) IN (A) IN (A) IN (A) IN (A) OUT A A H A OUT IN (N) IN (N) H IN (N) Z
D0-D7 RTS0 CTS0 DCD0 TXA0 RXA0
-- -- -- -- -- --
CKA0/DREQ0 CKA0 (Internal Clock Mode)
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Table 56.
Pin Status During RESET and LOW POWER OPERATION Modes (Continued) Pin Status in Each Operation Mode SYSTEM STOP IN (N) IN (N) H IN (N) Z IN (N) 1 H IN (N) IN (N) 1 Z IN (N) 1 0 1 1
Symbol
Pin Function CKA0 (External Clock Mode) DREQ0
RESET Z Z 1 IN (N) Z Z Z 1 IN (N) IN (N) Z Z IN (N) 1 1 1 1
SLEEP IN (A) IN (N) OUT IN (A) OUT IN (A) 1 OUT IN (A) IN (A) OUT IN (A) IN (N) 1 0 1 1
IOSTOP IN (N) IN (A) H IN (N) Z IN (N) OUT H IN (N) IN (N) 1 Z IN (A) OUT OUT OUT OUT
TXA1 RXA1
-- --
CKA1/TEND0 CKA1 (Internal Clock Mode) CKA1 (External Clock Mode) TEND0 TXS RXS/CTS 1 -- RXS CTS1 CKS CKS (Internal Clock Mode) CKS (External Clock Mode) DREQ1 TEND1 HALT RFSH IORQ -- -- -- -- --
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Table 56.
Pin Status During RESET and LOW POWER OPERATION Modes (Continued) Pin Status in Each Operation Mode SYSTEM STOP 1 1 1 1
Symbol MREQ E M1 WR RD Phi
Pin Function -- -- -- -- -- --
RESET 1 0 1 1 1
SLEEP 1 E Clock Output 1 1 1
IOSTOP OUT OUT OUT OUT
Phi Clock
Output
* * * *
1: HIGH 0: LOW A: Programmable Z: High Impedance IN (A): Input (Active) IN (N): Input (Not active) OUT: Output H: Holds the previous state
: same as the left
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I/O Registers
INTERNAL I/O REGISTERS
By programming IOA7 and IOA6 as the I/O control register, internal I/O register addresses are relocatable within ranges from0000H to 00FFH in the I/O address space.
Table 57. Register
ASCI Control Register A Channel 0:
Internal I/O Registers Remarks
bit during RESET R/W MPE 0 R/W RE 0 R/W TE 0 R/W RTS0 1 R/W MPBR/ EFR invalid R/W MOD2 MOD1 0 R/W 0 R/W MOD0 0 R/W
Mnemonics Address
CNTLA0 0 0
MODE Selection Multi Processor Bit Receive/ 1 Error Flag Reset Request to Send Transmit Enable Receive Enable Multi Processor Enable
ASCI Control Register A Channel 1:
CNTLA1
0
1
bit during RESET R/W MPE 0 R/W RE 0 R/W TE 0 R/W CKA1D 1 R/W
MPBR/ EFR invalid R/W
MOD2 MOD1 0 R/W 0 R/W
MOD0 0 R/W
MODE Selection Multi Processor Bit Receive/ Error Flag Reset CKA1 Disable Transmit Enable Receive Enable Multi Processor Enable MOD 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1
Start + 7 bit Data + 1 Stop Start + 7 bit Data + 2 Stop Start + 7 bit Data + Parity + 1 Stop Start + 7 bit Data + Parity + 2 Stop Start + 8 bit Data + 1 Stop Start + 8 bit Data + 2 Stop Start + 8 bit Data + Parity + 1 Stop Start + 8 bit Data + Parity + 2 Stop
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Table 57. Register
ASCI Control Register B Channel 0:
Internal I/O Registers (Continued) Remarks
bit during RESET R/W MPBT invalid R/W MP 0 R/W CTS/ PS * R/W PEO 0 R/W DR 0 R/W SS2 1 R/W SS1 1 R/W SS0 1 R/W
Mnemonics Address
CNTLB0 0 2
Divide Ratio Parity Even or Odd Clear to send/Prescale Multi Processor Multi Processor Bit Transmit * CTS: Depending on the condition 0f CTS Pin. PS: Cleared to 0.
Clock Source and Speed Select
ASCI Control Register B Channel 1:
CNTLB1
0
3
bit during RESET R/W MPBT invalid R/W MP 0 R/W CTS/ PS 0 R/W PEO 0 R/W DR 0 R/W SS2 1 R/W SS1 1 R/W SS0 1 R/W Clock Source and Speed Select Divide Ratio Parity Even or Odd Clear to Send/Prescale Multi Processor Multi Processor Bit Transmit
General divide ratio SS2 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
PS=0 (divide ratio=10) DR=0 (X 16) 160 / / 320 / 640 / 1280 / 2560 / 5120 / 10240 DR=1 (X 64) / / / / / / / 640 1280 2560 5120 10240 20480 40960
PS=1 (divide ratio=30) DR=0 (X 16) / / / / / / / 480 960 1920 3840 7680 15360 30720 DR=1 (X 64) / / / / / / / 1920 3840 7680 15360 30720 61440 122880
111
External clock (frequency < / 40)
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Table 57. Register
ASCI Status Channel 0:
Internal I/O Registers (Continued) Remarks
bit during RESET R/W RDRF 0 R OVRN 0 R PE 0 R FE 0 R RIE invalid R/W DCD0 * R TDRE ** R TIE 0 R/W Transmit Interrupt Enable Transmit Data Register Empty Data Carrier Detect Receive Interrupt Enable Framing Error Parity Error Overrun Error Receive Data Register Full * DCD0: Depending on the condition of DCD0 Pin.
Mnemonics Address
STAT0 0 4
** CTS0 Pin L H
TDRE 1 0
ASCI Status Channel 1:
STAT1
0
5
bit during RESET R/W RDRF 0 R OVRN 0 R PE 0 R FE 0 R 0 R/W RIE CTS1E TDRE 0 R 1 R TIE 0 R/W Transmit Interrupt Enable Transmit Data Register Empty CTS1 Enable Receive Interrupt Enable Framing Error Parity Error Overrun Error Receive Data Register Full
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Table 57. Register
ASCI Transmit Data Register Channel 0: ASCI Transmit Data Register Channel 1: ASCI Receive Data Register Channel 0: ASCI Receive Data Register Channel 1: CSI/O Control Register:
Internal I/O Registers (Continued) Remarks
Mnemonics Address
TDR0 0 6
TDR1
0
7
TSR0
0
8
TSR1
0
9
CNTR
0
A
bit during RESET R/W
EF 0 R
EIE 0 R/W
RE 0 R/W
TE 0 R/W
-- 1
SS2 1 R/W
SS1 1 R/W
SS0 1 R/W Speed Select
Transmit Enable Receive Enable End Interrupt Enable End Flag SS2 1 0 0 0 0 0 0 0 1 1 0 1 0 1 Baud Rate Phi / / / / 20 40 80 160 SS2 1 0 1 1 1 1 0 0 1 1 0 1 0 1 Baud Rate Phi / / / 320 640 1280
External frequency < / 20)
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Table 57. Register
CSI/O Transmit/ Receive Data Register: Timer Data Register Channel 0L: Timer Data Register Channel 0H: Timer Reload Register Channel 0L: Timer Reload Register Channel 0H: Timer Control Register Channel 0L:
Internal I/O Registers (Continued) Remarks
Mnemonics Address
TRDR 0 B
TMDR0L
0
C
TMDR0H
0
D
RLDR0L
0
E
RLDR0H
0
F
TCR
1
0
bit during RESET R/W
TF1 0 R
TF0 0 R
TE1 0 R/W
TE0 0 R/W
TOC1 0 R/W
TOC0 0 R/W
TDE1 0 R/W
TDE0 0 R/W
Timer Down Count Enable 1,0
Timer Output Control 1,0 Timer Interrupt Enable 1,0 Timer Interrupt Flag 1,0
TOC1,0 00 01 10 11
A18/TOUT Inhibited Toggle 0 1
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Table 57. Register
Timer Data Register Channel 1L: Timer Data Register Channel 1H: Timer Reload Register Channel 1L Timer Reload Register Channel 1H: Free Running Counter: DMA Source Address Register Channel 0L: DMA Source Address Register Channel 0H: DMA Source Address Register Channel 0B: DMA Destination Address Register Channel 0L: DMA Destination Address Register Channel 0H: DMA Destination Address Register Channel 0B: DMA Byte Count Register Channel 0L: DMA Byte Count Register Channel 0H: DMA Memory Address Register Channel 1L: DMA Memory Address Register Channel 1H:
Internal I/O Registers (Continued) Remarks
Mnemonics Address
TMDR1L TMDR1H RLDR1L RLDR1H FRC SAR0L SAR0H SAR0B DAR0L DAR0H DAR0B BCROL BCROH MAR1L 1 1 1 1 1 2 2 2 2 2 2 2 2 2 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Read only
Bits 0-2 (3) are used for SAR0B A19*, A18, A17, A16 X X X X X X X X 0 0 1 1 0 1 0 1
DMA Transfer Request
DREQ0 (external) RDR0 (ASCI0) RDR1 (ASCI1) Not used
Bits 0-2 (3) are used for DAR0B A19*, X X X X A18, X X X X A17, 0 0 1 1 A16 0 1 0 1
DMA Transfer Request
DREQ0 (external) TDR0 (ASCI0) TDR1 (ASCI1) Not used
MAR1H
2
9
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the package version of CP-68.
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Table 57. Register
DMA Memory Address Register Channel 1B:
Internal I/O Registers (Continued) Remarks
Bits 0 - 2 are used for MAR1B
Mnemonics Address
MAR1B 2 A
DMA I/O Address Register IAR1L Channel 1L: DMA I/O Address Register IAR1H Channel 1H DMA Byte Count Register BCR1L Channel 1L: DMA Byte Count Register Channel 1H: BCR1H DMA Status Register: DSTAT
2
B
2
C
2
E
2 3
F 0
bit during RESET R/W DE1 0 R/W DE0 0 R/W DWE1 DWE0 1 W 1 W DIE1 R/W 0 DIE0 0 R/W -- 1 DME 0 R DMA Master enable DMA Interrupt Enable 1,0
DMA Enable Bit Write Enable 1,0
DMA enable ch 1,0
DMA Mode Register:
DMODE
3
1
bit during RESET R/W -- 1 -- 1 DM1 0 R/W DM0 0 R/W SM1 0 R/W SM0 0 R/W MMOD 0 R/W Memory MODE select -- 1
Ch 0 Source Mode 1,0
Ch 0 Destination Mode 1,0
DM1,0 0 0 1 1 0 1 0 1 Mode Cycle Steal Mode Burst Mode Destination M M M I/O Address DAR0+1 DAR0-1 DAR0 fixed DAR0 fixed SM1,0 0 0 1 1 0 1 0 1 Source M M M I/O Address SAR0+1 SAR0-1 SAR0 fixed SAR0 fixed
MMOD 0 1
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Table 57. Register
MMU Common Base Register:
Internal I/O Registers (Continued) Remarks
bit during RESET R/W CB7 0 R/W CB6 0 R/W CB5 0 R/W CB4 0 R/W CB3 0 R/W CB2 0 R/W CB1 0 R/W CB0 0 R/W
Mnemonics Address
CBR 3 8
MMU Common Base Register
MMU Bank Base Register BBR
3
9
bit during RESET R/W
BB7 0 R/W
BB6 0 R/W
BB5 0 R/W
BB4 0 R/W
BB3 0 R/W
BB2 0 R/W
BB1 0 R/W
BB0 0 R/W
MMU Bank Base Register
MMU Common/Bank Register
CBAR
3
A
bit during RESET R/W CA3 1 R/W CA2 1 R/W CA1 1 R/W CA0 1 R/W BA3 0 R/W BA2 0 R/W BA1 0 R/W BA0 0 R/W
MMU Bank Area Register MMU Common Area Register
Operation Mode Control Register
OMCR
3
E
bit during RESET R/W
MIE 1 R/W
MITE 1 W
IOC 1 R/W
-- 1
-- 1
-- 1
-- 1
-- 1
I/O Compatibility M1 Temporary Enable M1 Enable
I/O Control Register:
ICR
3
F
bit during RESET R/W IOA7 0 R/W IOA6 0 R/W IOSTP 0 R/W I/O Stop -- 1 -- 1 -- 1 -- 1 -- 1
I/O Address
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Table 57. Register
DMA/WAIT Control Register:
Internal I/O Registers (Continued) Remarks
Mnemonics Address
DCNTL 3 2
bit during RESET R/W MWI1 1 R/W MWI0 1 R/W
IWI1 1 R/W
IWI0 1 R/W
DMS1 0 R/W
DMS0 0 R/W
DIMA1 DIMA0 0 R/W 0 R/W
DMA Ch 1 I/O Memory Mode Select I/O Wait Insertion Memory Wait Insertion The number of wait states 0 1 2 3
DREQi Select, i=1,0
MWI1,0 00 01 10 11
IWI1,0 00 01 10 11
The number of wait states 0 2 3 4
DMSi 1 0
Sense Edge sense Level sense
DIM1,0 00 01 10 11
Transfer Mode M I/O M I/O I/O M I/O M
Address Increment/Decrement MAR1+1 MAR1-1 IAR1 fixed IAR1 fixed IAR1 fixed IAR1 fixed MAR1+1 MAR1-1
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Table 57. Register
Interrupt Vector Low Register
Internal I/O Registers (Continued) Remarks
bit during RESET R/W IL7 0 R/W IL6 0 R/W IL5 0 R/W -- 0 -- 0 -- 0 -- 0 -- 0
Mnemonics Address
IL 3 3
Interrupt Vector Low
INT/TRAP Control Register
ITC
3
4
bit during RESET R/W
TRAP 0 R/W
UF0 0 R
-- 1
-- 1
-- 1
ITE2 0 R/W
ITE1 0 R/W
ITE0 0 R/W INT Enable 2,1,0
Unidentified Fetch Object TRAP
Refresh Control Register:
RCR
3
6
bit during RESET R/W
REFE 1 R/W
REFW 1 R/W
-- 1
-- 1
-- 1
-- 1
CYC1 0 R/W
CYC0 0 R/W
Cycle select Refresh Wait State Refresh Enable Interval of Refresh Cycle 00 01 10 11 10 states 20 40 80
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ORDERING INFORMATION Codes
*
Package P = Plastic Dip V = Plastic Chip Carrier F = Quad Flat Pack Temperature S = 0 to +70 C C E = -40 to 100 C C Speed 06 = 6 MHz 08 = 8 MHz 10 = 10 MHz Environmental C = Plastic Standard Example Z8018008PSC is an 80180 8 MHz, Plastic DIP, 0C to 70 Plastic Standard Flow. C,
Z 80180 08 P S C
* *
* *
Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix
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A
AC characteristics 197 Address generation, physical 64 Address map I/O 44 I/O address translation 57 Logical examples 55 Logical memory organization 58 Logical space configuration 59 Physical address transition 56 Addressing Extended 182 I/O 184 Indexed 182 Indirect 181 Architecture 12 ASCI Baud rate selection 142 Block diagram 117 Clock diagram 141 Control register A0 125 Control register A1 128 Control register B 131 Functions 116 Interrupt request circuit diagram 140 Register descriptions 117 Status register 0 120 Status register 1 123 Asynchronous serial communications interface (ASCI) 14
B
Baud rate selection ASCI 142 CSI/O 150 Block diagram 6 ASCI 117 CSI/O 146 DMAC 92 MMU 56 PRT 157 Bus state controller 13
C
Central processing unit (CPU) 14 Circuit diagram, ASCI interrupt request 140 Clock generator 13 Clocked serial I/O (CSI/O) 14 CPU register configurations 176 CPU timing Basic instruction 23 BUSREQ/BUSACK Bus Exchange 25 HALT and Low Power modes 31 I/O data read/write 22 Internal I/O registers 41 MMU register description 60 Op Code fetch timing 18 Operand and data read/write 20 RESET 25 Wait state generator 27
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CSI/O Baud rate selection 150 Block diagram 146 Control/Status register 147, 150, 159,
Direct register bit field definitions 181 Divide ratio DMA Controller (DMAC) 90 CYCLE STEAL mode timing diagram
134
160, 161, 172
External clock receivetiming diagram 156 External clock transmit timing diagram
106
Edge-sense timing diagram 108 Interrupt request generation 114 Level-sense timing diagram 107 Mode register (DMODE) 97 Operation 104 Status register (DSTAT) 95 TEND0 output timing diagram 108 Transfer request 110 WAIT control register 100 DMAC Block diagram 92 Register 93 DRAM refresh intervals 89 Dynamic RAM refresh control 86
154
Internal clock receivetiming diagram 155 Internal clock transmit timing diagram
153
interrupt request generation 151 Operation 151 Receive/Transmit timing diagram 204 Timer initialization, count down and reload timing diagram 163 Timer output control 163 Timer output timing diagram 164 Cycle timing
87
D
Data formats 131 DC characteristics Absolute maximum ratings 185 Z80180 186 Z8L180 189 Z8S180 187 DCD0 timing diagram 139 Description, general 1 Design rules, circuit board 170
E
E clock BUS RELEASE, SLEEP and SYSTEM STOP modes timing diagram 201 Memory and I/O R/W cycles timing diagram 201 Minimum timing example of PWEL and PWEH timing diagram 202 Timing conditions 166 Timing diagram (R/W and INTACK cy-
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cles)
167
INT0 Interrupt mode 2 timing 80 Mode 1 interrupt sequence 77 Mode 1 timing 78 INT0 mode 0 timing 76 Interrupt Acknowledge cycle timings 82 Control registers and flags 65 Controller 13 CSI/O request generation 151 DMA request generation 114 Enable (ITE) 68 INT/TRAP control register (ITC) 67 Maskable interrupt 0 (INT0) 75 Non-maskable 72 PRT request generation 164 Sources 65 Sources during reset 83 TRAP 70 Vector register (I) 66 IOSTOP mode 35
Timing diagram (SLEEP and SYSTEM STOP modes) 168 Extended addressing 182 External clock rise and fall time 204
F
Features
1
H
HALT mode
31
I
I/O Addressing 184 Control register (ICR) 42 I/O control register 42 Immediate addressing Addressing Immediate
183
Indexed addressing 182 Indirect addressing 181 Input ris and fall time (except EXTAL and RESET) timing diagram 204 Instruction set CPU registers 175 Flag register 178 Summary
L
Level-sense programming 109 Logical memory organization 58
M
M1 temporary enable timing 16 Maskable interrupt level 0 75
173
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Memory and I/O Wait state insertion 29 Memory management unit (MMU) 13
P
Pin description A0 through CTS1 7 BUSREQ through RFSH 9 D0 through INT2 8 RTS0 through TEND1 10 TEST through XTAL 10 Pin package 64-pin DIP 3 68-pin PLCC 4 80-pin QFP 5 Programmable reload timer (PRT) 14 Programming Level-sense PRT Block diagram 157 Bus release mode timing diagram 167 Interrupt request generation 164 Timer control register 161
109 Memory to memory 105
Memory to ASCI MMU Register description 60 Mode HALT 31 IOSTOP 35 SLEEP 33 SYSTEM STOP 35 Modem control signals 138
N
NMI and DMA operation timing diagram 115 Use 74 Non-maskable interrupt 72
109
O
On-chip clock generator Circuit board design rules 170 External clock interface 169 Operating frequencies 168 Operation modes Control register 84 CPU timing 18 IOC 16 M1 Enable 15 M1 temporary enable 16
R
Refresh
87
Control register 88 Register ASCI Control A0 125 ASCI Control A1 128 ASCI Control B 131 ASCI Status 0 120 ASCI Status 1 123
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CSI/O control/status 147, 150, 159,
160, 161, 172
Direct bit field definitions 181 DMA mode (DMODE) 97 DMA status 95 DMA/WAIT control 100 Flag 178 I/O Control 42 I/O control (ICR) 42 Indirect addressing 181 INT/TRAP control (ITC) 67 Interrupt Vector (I) 66 MMU bank base (BBR) 62 MMU common bank area (CBAR) 60 MMU common base (CBR) 61 Operation mode control 15, 84 PRT timer control register 161 Refresh control 88 Relative addressing Addressing Relative RETI control signal states 85 Instruction sequence 84 RTS0 timing diagram 140
Timing diagram SLP execution cycle 203 Status summary table 10 SYSTEM STOP mode 35
T
Test conditions, standard 205 Timer initialization, count down and reload
163
Timer output timing diagram Timing diagram Timer output 202 Timing diagram 163 AC 197 Bus Exchange Timing During CPU Internal Operation 27 Bus Exchange Timing During Memory Read 26 CPU (I/O Read/Write cycles) 199 CSI/O external clock receive 156 CSI/O external clock transmit 154 CSI/O internal clock receive 155 CSI/O internal clock transmit 153 CSI/O receive/transmit 204 CSI/O timer output 164 DCD0 139 DMA control signals 200 DMA CYCLE STEAL mode 106 DMA edge-sense 108 DMA level-sense 107
183
S
Secondary bus interface 165 SLEEP mode
33
SLP execution cycle timing diagram
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DMA TEND0 output 108 E clock (memory and I/O R/W cycles) 201 E clock (R/W and INTACK cycles) 167 E clock (SLEEP and SYSTEM STOP modes) 168 E clock BUS RELEASE, SLEEP and SYSTEM STOP modes) 201 E clock minimum timing example of PWEL and PWEH) 202 External clock rise and fall 204 HALT 33 I/O Read and Write cycles with IOC = 0 17 I/O read and write cycles with IOC=1 17 I/O read/write timing 23 Input rise and fall time 204 Instruction 24 INT0 interrupt mode 2 80 INT0 mode 0 76 INT0 mode 1 78 INT1, INT2 and Internal interrupts 86 M1 temporary enable 16 Memory read/write timing (with Wait state) 22 Memory read/write timing (without Wait state) 21 NMI and DMA operation 115 Op Code Fetch timing (with Wait state) 20 Op Code Fetch timing (without Wait state)
SLEEP
35
TRAP timing - 2nd Op Code Undefined 71 TRAP timing - 3rd Op Code Undefined 72 WAIT TRAP
28
68 71
Interrupt 70 Timing
U
Undefined Fetch Object (UFO) 68
V
Vector acquisition INT0 mode 2 INT1, INT2 Vector table 82
79
81
W
Wait state generation I/O Wait insertion Memory and
29
19
PRT bus release mode 167 Refresh cycle 87 RESET 25 RTS0 140
29
Programmable Wait state insertion 28 Wait input and reset 30 Wait state insertion 30
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